diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2020-09-15 15:37:44 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2021-11-02 16:50:32 +0800 |
| commit | de0501b9a08eb4d300620670cb44b0fd1bc2a8be (patch) | |
| tree | 2ccd06c11d759237b56640959bf3635e5d9d6539 /arch/arm64/boot/dts/freescale/imx8mp-evk.dts | |
| parent | 1af9d6bf0b19ff2b95d59734aaefad1b78a1aff8 (diff) | |
MLK-24171-1 arm64: dts: imx8mp: verify the pcie pll sys ref clock
Verify the PCIe PLL_SYS reference clock source on EVK board.
The external OSC clock is used as PCIe REF clock source in default.
NOTE: Change the ext_osc of pcie/pcie_phy to '0' when enable SYS_PLL
clock mode.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mp-evk.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index ce84630074d6..64b367cb0641 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -578,7 +578,7 @@ pinctrl-0 = <&pinctrl_pcie>; disable-gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; - ext_osc = <0>; + ext_osc = <1>; clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>, <&clk IMX8MP_CLK_PCIE_AUX>, <&clk IMX8MP_CLK_PCIE_PHY>, @@ -594,7 +594,7 @@ &pcie_ep{ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; - ext_osc = <0>; + ext_osc = <1>; clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>, <&clk IMX8MP_CLK_PCIE_AUX>, <&clk IMX8MP_CLK_PCIE_PHY>, @@ -608,6 +608,7 @@ }; &pcie_phy{ + ext_osc = <1>; status = "okay"; }; |