diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2020-05-27 10:11:08 +0800 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2020-11-26 13:51:58 +0000 |
| commit | dcec956f9168c7f9a902cd44bd9a577f850de5cc (patch) | |
| tree | 28174d39047454e49858128ccb126d3de6e18b4a /arch/arm64/boot/dts/freescale/imx8mp-evk.dts | |
| parent | e2e303b77b3f714687928e27f7a26a31f68a9b58 (diff) | |
MLK-24171-1 arm64: dts: imx8mp: verify the pcie pll sys ref clock
Verify the PCIe PLL_SYS reference clock source on EVK board.
The external OSC clock is used as PCIe REF clock source in default.
NOTE: Change the ext_osc of pcie/pcie_phy to '0' when enable SYS_PLL
clock mode.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
(cherry picked from commit 1bda33273eccae3c0d878d34660eca9da1765db0)
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mp-evk.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 062d7ca9f358..d4f616ffbba8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -650,7 +650,7 @@ pinctrl-0 = <&pinctrl_pcie>; disable-gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; - ext_osc = <0>; + ext_osc = <1>; clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>, <&clk IMX8MP_CLK_PCIE_AUX>, <&clk IMX8MP_CLK_PCIE_PHY>, @@ -665,6 +665,7 @@ }; &pcie_phy{ + ext_osc = <1>; status = "okay"; }; |