diff options
| author | Fancy Fang <chen.fang@nxp.com> | 2020-03-16 14:51:03 +0800 |
|---|---|---|
| committer | Fancy Fang <chen.fang@nxp.com> | 2020-04-27 16:29:34 +0800 |
| commit | daa7e137720b484cee9619c9c2a6a927f3a53698 (patch) | |
| tree | 908c13aa57177786e4d6e20865caa7ad6d2ea03f /arch/arm64/boot/dts/freescale/imx8mp.dtsi | |
| parent | 722638573e4094f8d2862cc7df2a8a0093ee5651 (diff) | |
MLK-23694-2 arm64: dts: imx8mp: assign 2079MHz to video_pll1
The 'video_pll1' clock is shared by MIPI and LVDS displays
and each of the display has a specific requirement for the
PLL rate which can be satified by set 'video_pll1' rate to
be 2079MHz. So assign 2079MHz rate to 'video_pll1' under
CCM device.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mp.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index e52b0992285d..6e90bb295be9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -692,7 +692,8 @@ <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>, <&clk IMX8MP_AUDIO_PLL1>, - <&clk IMX8MP_AUDIO_PLL2>; + <&clk IMX8MP_AUDIO_PLL2>, + <&clk IMX8MP_VIDEO_PLL1>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, <&clk IMX8MP_SYS_PLL1_800M>, <&clk IMX8MP_SYS_PLL2_500M>, @@ -705,7 +706,8 @@ <800000000>, <400000000>, <393216000>, - <361267200>; + <361267200>, + <2079000000>; }; src: src@30390000 { |