diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2020-05-27 10:11:08 +0800 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2020-11-26 13:51:58 +0000 |
| commit | dcec956f9168c7f9a902cd44bd9a577f850de5cc (patch) | |
| tree | 28174d39047454e49858128ccb126d3de6e18b4a /arch/arm64/boot/dts/freescale/imx8mp.dtsi | |
| parent | e2e303b77b3f714687928e27f7a26a31f68a9b58 (diff) | |
MLK-24171-1 arm64: dts: imx8mp: verify the pcie pll sys ref clock
Verify the PCIe PLL_SYS reference clock source on EVK board.
The external OSC clock is used as PCIe REF clock source in default.
NOTE: Change the ext_osc of pcie/pcie_phy to '0' when enable SYS_PLL
clock mode.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
(cherry picked from commit 1bda33273eccae3c0d878d34660eca9da1765db0)
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mp.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 3e214af2ae27..bf8f838972a0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1936,7 +1936,7 @@ <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; - fsl,max-link-speed = <3>; + fsl,max-link-speed = <2>; power-domains = <&pcie_pd>; resets = <&src IMX8MQ_RESET_PCIEPHY>, <&src IMX8MQ_RESET_PCIEPHY_PERST>, |