diff options
| author | Fancy Fang <chen.fang@nxp.com> | 2021-02-18 10:36:24 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2021-11-02 16:51:07 +0800 |
| commit | bf3300a29a0dbbf0686634f2101fd9e0ba2f2be8 (patch) | |
| tree | 9c362989acff0d10b7a8b4e6ba0a0f3d6a22032b /arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-rm67191.dts | |
| parent | 2f86702a18c1cf6e25e70611385f81407bb5ae7b (diff) | |
LF-3386 arm64: imx8mq-evk-dcss-rm67191: config disp_apb properly
After reduce the panel RM67191's pixel clock from 132MHz to
121MHz by 'commit 4193a9c3254b ("MLK-3056-2 drm/panel: rm67191:
change clock rate to 121MHz for default mod")', the disp_apb
clock rate needs to be configured properly to avoid the issue
described in LF-33886 ticket with currrent disp_apb clock config
like below:
sys1_pll_out 5 5 0 800000000 0 0 50000
sys1_pll_800m 5 5 0 800000000 0 0 50000
disp_apb 1 1 0 133333334 0 0 50000
disp_apb_root_clk 2 2 0 133333334 0 0 50000
And configure disp_apb rate to 25MHz like below can solve this
issue:
sys1_pll_out 5 5 0 800000000 0 0 50000
sys1_pll_800m 5 5 0 800000000 0 0 50000
disp_apb 1 1 0 25000000 0 0 50000
disp_apb_root_clk 2 2 0 25000000 0 0 50000
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-rm67191.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-rm67191.dts | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-rm67191.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-rm67191.dts index 333fe916d681..a49332ce4876 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-rm67191.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-rm67191.dts @@ -28,14 +28,17 @@ <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, <&clk IMX8MQ_CLK_DISP_AXI>, + <&clk IMX8MQ_CLK_DISP_APB>, <&clk IMX8MQ_CLK_DISP_RTRM>; assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, <&clk IMX8MQ_VIDEO_PLL1>, <&clk IMX8MQ_CLK_27M>, <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_SYS1_PLL_800M>; assigned-clock-rates = <600000000>, <0>, <0>, <800000000>, + <25000000>, <400000000>; port@0 { |