diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2020-12-30 13:50:50 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2021-11-02 16:50:57 +0800 |
| commit | a09c24ed6c0dbe73491af8b7ef8d5a8fb5c862ad (patch) | |
| tree | 346aab683e1bbaa14baf99f96853dadc8efa5ee9 /arch/arm64/boot/dts/freescale/imx8mq-evk.dts | |
| parent | e9a14811b5176b59131b56873839f52e3bd3da76 (diff) | |
MLK-25915-1 arm64: dts: imx8m: set the parent clock of pcie aux clock
Set the parent clock for PCIE_AUX clock firstly, then set the rate of
the PCI_AUX clock to 10MHZ.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Peter Chen <peter.chen@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mq-evk.dts')
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index e516bc32c65a..4ff9208dd269 100755 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -631,6 +631,9 @@ <&pcie0_refclk>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; vph-supply = <&vgen5_reg>; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_AUX>; + assigned-clock-rates = <10000000>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_50M>; hard-wired = <1>; status = "okay"; }; @@ -645,6 +648,9 @@ <&clk IMX8MQ_CLK_PCIE2_PHY>, <&pcie1_refclk>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_AUX>; + assigned-clock-rates = <10000000>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_50M>; status = "okay"; }; @@ -656,6 +662,9 @@ <&clk IMX8MQ_CLK_PCIE2_PHY>, <&pcie1_refclk>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_AUX>; + assigned-clock-rates = <10000000>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_50M>; status = "disabled"; }; |