diff options
| author | Clark Wang <xiaoning.wang@nxp.com> | 2022-05-26 17:22:45 +0800 |
|---|---|---|
| committer | Clark Wang <xiaoning.wang@nxp.com> | 2022-07-11 18:08:04 +0800 |
| commit | baec80ba1cf4f0fe81783a6afa28972e3b129f69 (patch) | |
| tree | 35fccb95690b992fead3ef4a80592819a8f7e089 /arch/arm64/boot/dts/freescale/imx93-11x11-evk-i3c.dts | |
| parent | 4dee10c3e1c57267059dbc5e067b3f3ef4f8df0e (diff) | |
MLK-25922-5 arm64: dts: imx93: add i3c support
Add I3C support.
Enable I3C1 bus and replace I2C1.
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
(cherry picked from commit cfe9f5c34ea074e73004f8331328aff24af2dd5a)
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx93-11x11-evk-i3c.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx93-11x11-evk-i3c.dts | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk-i3c.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk-i3c.dts new file mode 100644 index 000000000000..c91fb5785cce --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk-i3c.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx93-11x11-evk.dts" + +/{ + aliases { + /delete-property/ i2c0; + }; +}; + +/delete-node/&lpi2c1; + +/* + * When add i2c devices on i3c bus, the reg property should be changed to: + * reg = <0x1a 0x00 0x50>; + * The first byte is still the address of the i2c device; + * The second byte is always 0x00; + * The third byte is the communication speed of this i2c device; + * 0x20 means 1MHz(FM+); + * 0x50 means 400KHz(FM); + * In compatibility mode, I3C will use the slowest setting of all targets + * for i2c communication. + */ +&i3c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_i3c1>; + pinctrl-1 = <&pinctrl_i3c1>; + i2c-scl-hz = <400000>; + status = "okay"; + + /* i3c device with static i2c address*/ + lsm6dso_i3c: imu@6a,208006c0000 { + reg = <0x6a 0x208 0x6c0000>; + assigned-address = <0x6a>; + }; + + /* i2c devices */ +}; + +&iomuxc { + pinctrl_i3c1: i3c1grp { + fsl,pins = < + MX93_PAD_I2C1_SCL__I3C1_SCL 0x4000019e + MX93_PAD_I2C1_SDA__I3C1_SDA 0x4000019e + >; + }; +};
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