diff options
| author | Joakim Zhang <qiangqing.zhang@nxp.com> | 2020-09-02 17:13:48 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2021-11-02 16:50:32 +0800 |
| commit | cb983a174dea56b6aa41395fbbe38ce8c8688641 (patch) | |
| tree | 3338c3ccf41ae4badf99a56b7d8f3a90cf3b6606 /arch/arm64/boot/dts/freescale | |
| parent | 4c841357ca8ec31af01791622db7893a0d80a998 (diff) | |
MLK-24752-1 arch: arm64: imx8m: add IR support
Add IR support for i.MX8MM/MN/MQ.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 13 | ||||
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 13 |
2 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index b5e0e8d1eea3..e275beb300f0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -36,6 +36,13 @@ #reset-cells = <0>; }; + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ir_recv>; + }; + usdhc1_pwrseq: usdhc1_pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; @@ -541,6 +548,12 @@ >; }; + pinctrl_ir_recv: ir-recv { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 0ceabfa8524e..71a60a77a40b 100755 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -41,6 +41,13 @@ #reset-cells = <0>; }; + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ir_recv>; + }; + resmem: reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -875,6 +882,12 @@ >; }; + pinctrl_ir_recv: ir-recv { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x4f + >; + }; + pinctrl_csi1_pwn: csi1_pwn_grp { fsl,pins = < MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 |