diff options
| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2022-03-24 15:03:41 +0100 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2022-03-24 15:52:22 +0100 |
| commit | 60d2765d720c87af68788d83b21cbc0c4a60a17a (patch) | |
| tree | 58cb2023413c46790e10c0f489f63124f202d774 /arch/arm64/boot/dts/freescale | |
| parent | 7f8d7f97ebd50d080098be0758ef91234932db52 (diff) | |
arm64: dts: imx8mp-verdin: add sd1 sleep pinctrl
Add SD1 sleep pinctrl to avoid backfeeding during sleep.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale')
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index 022e5435b221..be5b89a89157 100755 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -850,10 +850,11 @@ bus-width = <4>; cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; disable-wp; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; vmmc-supply = <®_usdhc2_vmmc>; }; @@ -1352,6 +1353,12 @@ >; }; + pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0 /* SODIMM 84 */ + >; + }; + pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { fsl,pins = < MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x4 /* SODIMM 76 */ @@ -1394,6 +1401,19 @@ >; }; + /* Avoid backfeeding with removed card power */ + pinctrl_usdhc2_sleep: usdhc2slpgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x100 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x100 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x100 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x100 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x100 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x100 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x0 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 |