arm64: dts: imx8qxp: enable enet2 port for MEK board

Enable enet2 port for MEK board.

Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
[ Aisheng: fix small conflicts during upgrade ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

6 files changed, 150 insertions, 6 deletions

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index ec8a0df500c4..5cdb06b0f80b 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -32,4 +32,5 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb imx8qm-mek-max9286.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
-dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb imx8qxp-mek-dsp.dtb imx8qxp-mek-max9286.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb imx8qxp-mek-dsp.dtb imx8qxp-mek-max9286.dtb \
+			  imx8qxp-mek-enet2.dtb imx8qxp-mek-enet2-tja1100.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
index 163eefa9a9c9..68c79baa80bf 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
@@ -108,8 +108,9 @@ conn_subsys: bus@5b000000 {
 		clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>,
 			 <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>,
 			 <&conn_lpcg IMX_CONN_LPCG_ENET0_RGMII_TXC_CLK>,
-			 <&conn_lpcg IMX_CONN_LPCG_ENET0_TIMER_CLK>;
-		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
+			 <&conn_lpcg IMX_CONN_LPCG_ENET0_TIMER_CLK>,
+			 <&conn_lpcg IMX_CONN_LPCG_ENET0_TXC_SAMPLING_CLK>;
+		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
 		assigned-clocks = <&clk IMX_CONN_ENET0_ROOT_CLK>,
 				  <&clk IMX_CONN_ENET0_REF_DIV>;
 		assigned-clock-rates = <250000000>, <125000000>;
@@ -129,8 +130,9 @@ conn_subsys: bus@5b000000 {
 		clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>,
 			 <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>,
 			 <&conn_lpcg IMX_CONN_LPCG_ENET1_RGMII_TXC_CLK>,
-			 <&conn_lpcg IMX_CONN_LPCG_ENET1_TIMER_CLK>;
-		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
+			 <&conn_lpcg IMX_CONN_LPCG_ENET1_TIMER_CLK>,
+			 <&conn_lpcg IMX_CONN_LPCG_ENET1_TXC_SAMPLING_CLK>;
+		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
 		assigned-clocks = <&clk IMX_CONN_ENET1_ROOT_CLK>,
 				  <&clk IMX_CONN_ENET1_REF_DIV>;
 		assigned-clock-rates = <250000000>, <125000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-enet2-tja1100.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-enet2-tja1100.dtsi
new file mode 100644
index 000000000000..dd363d61efb8
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-enet2-tja1100.dtsi
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&fec1 {
+	status = "disabled";
+};
+
+&fec2 {
+	pinctrl-0 = <&pinctrl_fec2_rmii>;
+	clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>,
+		 <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>,
+		 <&conn_lpcg IMX_CONN_LPCG_ENET1_RGMII_TXC_CLK>,
+		 <&conn_lpcg IMX_CONN_LPCG_ENET1_RMII_REF_50MHZ_CLK>,
+		 <&conn_lpcg IMX_CONN_LPCG_ENET1_TXC_SAMPLING_CLK>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy2>;
+	/delete-property/ phy-supply;
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy2: ethernet-phy@5 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <5>;
+			tja110x,refclk_in;
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl_fec2_rmii: fec2rmiigrp {
+		fsl,pins = <
+			IMX8QXP_ENET0_MDC_CONN_ENET1_MDC		0x06000020
+			IMX8QXP_ENET0_MDIO_CONN_ENET1_MDIO		0x06000020
+			IMX8QXP_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT	0x06000020
+			IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0		0x06000020
+			IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1	0x06000020
+			IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER	0x06000020
+			IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL	0x06000020
+			IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0	0x06000020
+			IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1	0x06000020
+			IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL	0x06000020
+		>;
+	};
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2-tja1100.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2-tja1100.dts
new file mode 100644
index 000000000000..7651dc6fa682
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2-tja1100.dts
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "imx8qxp-mek-enet2.dts"
+#include "imx8qxp-enet2-tja1100.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2.dts
new file mode 100644
index 000000000000..3f7daa62f740
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2.dts
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "imx8qxp-mek.dts"
+
+&adma_esai0 {
+	status = "disabled";
+};
+
+&ethphy1 {
+	status = "okay";
+};
+
+&fec2 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index 314d18bae7d8..1b1b1e7c31f8 100755
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -107,6 +107,15 @@
 		vin-supply = <&reg_can_en>;
 	};
 
+	reg_fec2_supply: fec2_nvcc {
+		compatible = "regulator-fixed";
+		regulator-name = "fec2_nvcc";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
 	reg_usb_otg1_vbus: regulator-usbotg1-vbus {
 		compatible = "regulator-fixed";
 		regulator-name = "usb_otg1_vbus";
@@ -450,11 +459,12 @@
 &fec1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_fec1>;
-	phy-mode = "rgmii-id";
+	phy-mode = "rgmii-txid";
 	phy-handle = <&ethphy0>;
 	fsl,magic-packet;
 	nvmem-cells = <&fec_mac0>;
 	nvmem-cell-names = "mac-address";
+	fsl,rgmii_rxc_dly;
 	status = "okay";
 
 	mdio {
@@ -473,10 +483,24 @@
 			reg = <1>;
 			at803x,eee-disabled;
 			at803x,vddio-1p8v;
+			status = "disabled";
 		};
 	};
 };
 
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec2>;
+	phy-mode = "rgmii-txid";
+	phy-handle = <&ethphy1>;
+	phy-supply = <&reg_fec2_supply>;
+	fsl,magic-packet;
+	nvmem-cells = <&fec_mac1>;
+	nvmem-cell-names = "mac-address";
+	fsl,rgmii_rxc_dly;
+	status = "disabled";
+};
+
 &flexspi0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_flexspi0>;
@@ -849,6 +873,23 @@
 		>;
 	};
 
+	pinctrl_fec2: fec2grp {
+		fsl,pins = <
+			IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL	0x00000060
+			IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC		0x00000060
+			IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0	0x00000060
+			IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1	0x00000060
+			IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2		0x00000060
+			IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3	0x00000060
+			IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC		0x00000060
+			IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL	0x00000060
+			IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0		0x00000060
+			IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1	0x00000060
+			IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2	0x00000060
+			IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3		0x00000060
+		>;
+	};
+
 	pinctrl_flexspi0: flexspi0grp {
 		fsl,pins = <
 			IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0     0x06000021