arm64: dts: add imx8qxp gpmi-nand dts

add gpmi-nand dts for nand support on imx8qxp val

Signed-off-by: Han Xu <han.xu@nxp.com>

3 files changed, 122 insertions, 2 deletions

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 3cbb6fa13830..f4e6c9eb8683 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -54,5 +54,5 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb imx8qxp-mek-dsp.dtb imx8qxp-mek-ov5640
 			  imx8qxp-mek-rpmsg.dtb imx8qxp-mek-a0.dtb imx8qxp-lpddr4-val-a0.dtb \
 			  imx8qxp-lpddr4-val.dtb imx8qxp-lpddr4-val-mqs.dtb imx8qxp-ddr3l-val.dtb \
 			  imx8qxp-lpddr4-val-lpspi.dtb imx8qxp-lpddr4-val-lpspi-slave.dtb \
-			  imx8qxp-lpddr4-val-spdif.dtb imx8dxp-lpddr4-val.dtb imx8qxp-17x17-val.dtb \
-			  imx8dx-lpddr4-val.dtb imx8dx-17x17-val.dtb
+			  imx8qxp-lpddr4-val-spdif.dtb imx8qxp-lpddr4-val-gpmi-nand.dtb imx8dxp-lpddr4-val.dtb \
+			  imx8qxp-17x17-val.dtb imx8dx-lpddr4-val.dtb imx8dx-17x17-val.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
index f23d45f1ee87..ff7f95017468 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
@@ -33,6 +33,13 @@ conn_subsys: bus@5b000000 {
 		clock-output-names = "conn_ipg_clk";
 	};
 
+	conn_bch_clk: clock-conn-bch {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <400000000>;
+		clock-output-names = "conn_bch_clk";
+	};
+
 	usbotg1: usb@5b0d0000 {
 		compatible = "fsl,imx8qm-usb", "fsl,imx7ulp-usb",
 			"fsl,imx27-usb";
@@ -293,4 +300,67 @@ conn_subsys: bus@5b000000 {
 				     "usb3_aclk";
 		power-domains = <&pd IMX_SC_R_USB_2_PHY>;
 	};
+
+	rawnand_0_lpcg: clock-controller@5b290000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5b290000 0x4>;
+		#clock-cells = <1>;
+		clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_PER>,
+			 <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>,
+			 <&conn_axi_clk>,
+			 <&conn_axi_clk>;
+		bit-offset = <0 4 16 20>;
+		clock-output-names = "bch_clk",
+				     "gpmi_clk",
+				     "gpmi_apb_clk",
+				     "bch_apb_clk";
+		power-domains = <&pd IMX_SC_R_NAND>;
+	};
+
+	rawnand_4_lpcg: clock-controller@5b290004 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5b290004 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&conn_axi_clk>;
+		bit-offset = <16>;
+		clock-output-names = "apbhdma_hclk";
+		power-domains = <&pd IMX_SC_R_NAND>;
+	};
+
+	dma_apbh: dma-apbh@5b810000 {
+		compatible = "fsl,imx28-dma-apbh";
+		reg = <0x5b810000 0x2000>;
+		interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
+		#dma-cells = <1>;
+		dma-channels = <4>;
+		clocks = <&rawnand_4_lpcg 0>;
+		clock-names = "apbhdma_hclk";
+		power-domains = <&pd IMX_SC_R_NAND>;
+	};
+
+	gpmi: gpmi-nand@5b812000{
+		compatible = "fsl,imx8qxp-gpmi-nand";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x5b812000 0x2000>, <0x5b814000 0x2000>;
+		reg-names = "gpmi-nand", "bch";
+		interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "bch";
+		clocks = <&rawnand_0_lpcg 1>,
+			 <&rawnand_0_lpcg 2>,
+			 <&rawnand_0_lpcg 0>,
+			 <&rawnand_0_lpcg 3>;
+		clock-names = "gpmi_clk", "gpmi_apb_clk",
+			      "bch_clk", "bch_apb_clk";
+		dmas = <&dma_apbh 0>;
+		dma-names = "rx-tx";
+		power-domains = <&pd IMX_SC_R_NAND>;
+		assigned-clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>;
+		assigned-clock-rates = <50000000>;
+		status = "disabled";
+	};
 };
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-gpmi-nand.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-gpmi-nand.dts
new file mode 100644
index 000000000000..369c942694e6
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-gpmi-nand.dts
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017 NXP
+ */
+
+#include "imx8qxp-lpddr4-val.dts"
+
+&iomuxc {
+	pinctrl_gpmi_nand_1: gpmi-nand-1 {
+		fsl,pins = <
+			IMX8QXP_EMMC0_CLK_CONN_NAND_READY_B	0x0e00004c
+			IMX8QXP_EMMC0_DATA0_CONN_NAND_DATA00	0x0e00004c
+			IMX8QXP_EMMC0_DATA1_CONN_NAND_DATA01	0x0e00004c
+			IMX8QXP_EMMC0_DATA2_CONN_NAND_DATA02	0x0e00004c
+			IMX8QXP_EMMC0_DATA3_CONN_NAND_DATA03	0x0e00004c
+			IMX8QXP_EMMC0_DATA4_CONN_NAND_DATA04	0x0e00004c
+			IMX8QXP_EMMC0_DATA5_CONN_NAND_DATA05	0x0e00004c
+			IMX8QXP_EMMC0_DATA6_CONN_NAND_DATA06	0x0e00004c
+			IMX8QXP_EMMC0_DATA7_CONN_NAND_DATA07	0x0e00004c
+			IMX8QXP_EMMC0_STROBE_CONN_NAND_CLE		0x0e00004c
+			IMX8QXP_EMMC0_RESET_B_CONN_NAND_WP_B	0x0e00004c
+
+			IMX8QXP_USDHC1_DATA0_CONN_NAND_CE1_B	0x0e00004c
+			IMX8QXP_USDHC1_DATA2_CONN_NAND_WE_B	0x0e00004c
+			IMX8QXP_USDHC1_DATA3_CONN_NAND_ALE		0x0e00004c
+			IMX8QXP_USDHC1_CMD_CONN_NAND_CE0_B		0x0e00004c
+
+			/* i.MX8QXP NAND use nand_re_dqs_pins */
+			IMX8QXP_USDHC1_CD_B_CONN_NAND_DQS	0x0e00004c
+			IMX8QXP_USDHC1_VSELECT_CONN_NAND_RE_B	0x0e00004c
+
+		>;
+	};
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+	status = "okay";
+	nand-on-flash-bbt;
+};
+
+/* Disabled the usdhc1/usdhc2 since pin conflict */
+&usdhc1 {
+	status = "disabled";
+};
+
+&usdhc2 {
+	status = "disabled";
+};