diff options
author | Richard Zhu <hongxing.zhu@nxp.com> | 2020-09-14 14:20:13 +0800 |
---|---|---|
committer | Dong Aisheng <aisheng.dong@nxp.com> | 2021-11-02 16:50:32 +0800 |
commit | 1af9d6bf0b19ff2b95d59734aaefad1b78a1aff8 (patch) | |
tree | dbcbdb96f59ee97c875ad3ab4cf90ed29ba8645b /arch/arm64/boot | |
parent | cb983a174dea56b6aa41395fbbe38ce8c8688641 (diff) |
MLK-24012-06 arm64: dts: add imx8m pcie ep support
Add the PCIe EP mode on iMX8MQ/MM/MP platforms.
And enable the EP mode on EVK boards.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Diffstat (limited to 'arch/arm64/boot')
-rw-r--r-- | arch/arm64/boot/dts/freescale/Makefile | 2 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-pcie-ep.dts | 16 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mm-evk-pcie-ep.dts | 16 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dts | 16 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 16 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp.dtsi | 24 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mq-evk-pcie-ep.dts | 20 | ||||
-rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 11 | ||||
-rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8mq.dtsi | 19 |
9 files changed, 140 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 28ef868e5a5a..8e317c91815f 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb imx8mn-ddr4-evk-ak5558.dtb imx8mn- dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb imx8mp-evk-rm67191.dtb imx8mp-evk-it6263-lvds-dual-channel.dtb \ + imx8mp-evk-pcie-ep.dtb \ imx8mp-evk-jdi-wuxga-lvds-panel.dtb imx8mp-evk-flexcan2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb imx8mq-evk-rpmsg.dtb @@ -75,6 +76,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-dp.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-ddr3l-val.dtb imx8mq-ddr4-val.dtb imx8mq-ddr4-val-gpmi-nand.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-pcie-ep.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-pcie-ep.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-pcie-ep.dts new file mode 100644 index 000000000000..da61f5b76d26 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-pcie-ep.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mm-ddr4-evk.dts" + +&pcie0{ + status = "disabled"; +}; + +&pcie0_ep{ + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk-pcie-ep.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk-pcie-ep.dts new file mode 100644 index 000000000000..2f96420e3230 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk-pcie-ep.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mm-evk.dts" + +&pcie0{ + status = "disabled"; +}; + +&pcie0_ep{ + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dts new file mode 100644 index 000000000000..3ed4f2121e5a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mp-evk.dts" + +&pcie{ + status = "disabled"; +}; + +&pcie_ep{ + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 516857deb538..ce84630074d6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -591,6 +591,22 @@ status = "okay"; }; +&pcie_ep{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + ext_osc = <0>; + clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>, + <&clk IMX8MP_CLK_PCIE_AUX>, + <&clk IMX8MP_CLK_PCIE_PHY>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>, + <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL2_50M>; + status = "disabled"; +}; + &pcie_phy{ status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 455ffc3b3f69..09b9417753cd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1961,6 +1961,30 @@ status = "disabled"; }; + pcie_ep: pcie_ep@33800000 { + compatible = "fsl,imx8mp-pcie-ep"; + reg = <0x0 0x33800000 0x0 0x000400000>, + <0x0 0x18000000 0x0 0x08000000>; + reg-names = "regs", "addr_space"; + num-lanes = <1>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ + interrupt-names = "dma"; + fsl,max-link-speed = <3>; + power-domains = <&pcie_pd>; + resets = <&src IMX8MQ_RESET_PCIEPHY>, + <&src IMX8MQ_RESET_PCIEPHY_PERST>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "pciephy_perst", "apps", "clkreq", "turnoff"; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + fsl,imx8mp-hsio-mix = <&hsio_mix>; + num-ib-windows = <4>; + num-ob-windows = <4>; + status = "disabled"; + }; + ddr-pmu@3d800000 { compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu"; reg = <0x3d800000 0x400000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-pcie-ep.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-pcie-ep.dts new file mode 100644 index 000000000000..7534041490c7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-pcie-ep.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mq-evk.dts" + +&pcie0{ + status = "disabled"; +}; + +&pcie1{ + status = "disabled"; +}; + +&pcie1_ep{ + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 71a60a77a40b..8d57722de060 100755 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -677,6 +677,17 @@ status = "okay"; }; +&pcie1_ep { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&pcie1_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + status = "disabled"; +}; + &pgc_gpu { power-supply = <&sw1a_reg>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 8e9921d8b98f..198a22f93382 100755 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1575,6 +1575,25 @@ status = "disabled"; }; + pcie1_ep: pcie_ep@33c00000 { + compatible = "fsl,imx8mq-pcie-ep"; + reg = <0x33c00000 0x000400000>, + <0x20000000 0x08000000>; + reg-names = "regs", "addr_space"; + num-lanes = <1>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ + interrupt-names = "dma"; + fsl,max-link-speed = <2>; + power-domains = <&pgc_pcie>; + resets = <&src IMX8MQ_RESET_PCIEPHY2>, + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "turnoff"; + num-ib-windows = <4>; + num-ob-windows = <4>; + status = "disabled"; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, /* GIC Dist */ |