diff options
| author | Suzuki K Poulose <suzuki.poulose@arm.com> | 2018-07-04 23:07:46 +0100 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2018-07-05 10:20:59 +0100 |
| commit | 314d53d297980676011e6fd83dac60db4a01dc70 (patch) | |
| tree | 201eddf7774afbd9ef20845a69f091aeef94e056 /arch/arm64/include/asm/cpucaps.h | |
| parent | 4c4a39dd5fe2d13e2d2fa5fceb8ef95d19fc389a (diff) | |
arm64: Handle mismatched cache type
Track mismatches in the cache type register (CTR_EL0), other
than the D/I min line sizes and trap user accesses if there are any.
Fixes: be68a8aaf925 ("arm64: cpufeature: Fix CTR_EL0 field definitions")
Cc: <stable@vger.kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/cpucaps.h')
| -rw-r--r-- | arch/arm64/include/asm/cpucaps.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index 8a699c708fc9..be3bf3d08916 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -49,7 +49,8 @@ #define ARM64_HAS_CACHE_DIC 28 #define ARM64_HW_DBM 29 #define ARM64_SSBD 30 +#define ARM64_MISMATCHED_CACHE_TYPE 31 -#define ARM64_NCAPS 31 +#define ARM64_NCAPS 32 #endif /* __ASM_CPUCAPS_H */ |