diff options
| author | Catalin Marinas <catalin.marinas@arm.com> | 2014-03-24 10:35:35 +0000 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2014-03-24 10:35:35 +0000 |
| commit | 196adf2f3015eacac0567278ba538e3ffdd16d0e (patch) | |
| tree | 2dc6514b3263a9f3ed69b3b0ff34ef908afa5af7 /arch/arm64/include/asm/pgtable.h | |
| parent | 214fdbe74a096c3aeb7af81d7900e2ab966b10d6 (diff) | |
arm64: Remove pgprot_dmacoherent()
Since this macro is identical to pgprot_writecombine() and is only used
in a single place, remove it completely to avoid confusion. On ARMv7+
processors, the coherent DMA mapping must be Normal NonCacheable (a.k.a.
writecombine) to avoid mismatched hardware attribute aliases (with the
kernel linear mapping as Normal Cacheable).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/pgtable.h')
| -rw-r--r-- | arch/arm64/include/asm/pgtable.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index ae10350f75ec..da92265bd798 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -280,8 +280,6 @@ static inline int has_transparent_hugepage(void) __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) #define pgprot_writecombine(prot) \ __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) -#define pgprot_dmacoherent(prot) \ - __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) #define __HAVE_PHYS_MEM_ACCESS_PROT struct file; extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, |