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authorPhilippe Schenker <philippe.schenker@toradex.com>2020-01-31 13:30:29 +0100
committerPhilippe Schenker <philippe.schenker@toradex.com>2020-02-03 09:54:09 +0100
commit40f60264c7f8772d24283c17848dd099198a4cff (patch)
tree28a865b2eba80793e4143f6a22dc542d4a099efa /arch/arm64
parent2141ab0f3b4e36b01ed37c2748868ca0cce2273e (diff)
ARM64: dts: apalis-imx8qm: add sleep-mode to fec
Note: there is still backfeeding present at this moment from those pads: SC_P_ENET0_RGMII_TXD0 SC_P_ENET0_RGMII_TXD1 SC_P_ENET0_RGMII_RXD0 SC_P_ENET0_RGMII_RXD1 Related-to: ELB-1254 Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Diffstat (limited to 'arch/arm64')
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dtsi26
1 files changed, 25 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dtsi
index 655cfffa4e19..4abdb8a4ba7b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dtsi
@@ -228,8 +228,9 @@
/* Apalis GLAN */
&fec1 {
- pinctrl-names = "default";
+ pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_fec1>;
+ pinctrl-1 = <&pinctrl_fec1_sleep>;
fsl,magic-packet;
fsl,rgmii_rxc_dly;
fsl,rgmii_txc_dly;
@@ -1022,6 +1023,29 @@
>;
};
+ pinctrl_fec1_sleep: fec1-sleepgrp {
+ fsl,pins = <
+ SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0
+ SC_P_ENET0_MDC_LSIO_GPIO4_IO14 0x04000040
+ SC_P_ENET0_MDIO_LSIO_GPIO4_IO13 0x04000040
+ SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31 0x04000040
+ SC_P_ENET0_RGMII_TXC_LSIO_GPIO5_IO30 0x04000040
+ SC_P_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00 0x04000040
+ SC_P_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01 0x04000040
+ SC_P_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02 0x04000040
+ SC_P_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03 0x04000040
+ SC_P_ENET0_RGMII_RXC_LSIO_GPIO6_IO04 0x04000040
+ SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05 0x04000040
+ SC_P_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06 0x04000040
+ SC_P_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07 0x04000040
+ SC_P_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08 0x04000040
+ SC_P_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09 0x04000040
+ SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15 0x04000040
+ SC_P_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x04000040
+ SC_P_LVDS0_GPIO01_LSIO_GPIO1_IO05 0x04000040
+ >;
+ };
+
/* On-module HDMI_CTRL */
pinctrl_hdmi_ctrl: hdmictrlgrp {
fsl,pins = <