diff options
| author | Max Krummenacher <max.krummenacher@toradex.com> | 2020-11-24 20:28:07 +0100 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2020-11-25 10:44:03 +0100 |
| commit | 3808f2b30c8fc10271ceace1cbe79bc2108b0a33 (patch) | |
| tree | 6207bcea569b64e25419fb1000756fa11a15200a /arch/arm64 | |
| parent | 4e2da15e0895228c07039968d396a931c9de82b2 (diff) | |
arm64: dts: imx8mp-verdin: fix eqos mac
With the driver now supporting the phy-supply property, remove the
regulator-boot-on property.
The driver does not support the 'sleep' state pinctrl. Remove it.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Diffstat (limited to 'arch/arm64')
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi | 24 |
1 files changed, 1 insertions, 23 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index 3368054b77ed..65009364d6f1 100755 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -60,7 +60,6 @@ off-on-delay = <500000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_eth>; - regulator-boot-on; regulator-max-microvolt = <3300000>; regulator-min-microvolt = <3300000>; regulator-name = "V3.3_ETH"; @@ -166,9 +165,8 @@ phy-handle = <ðphy0>; phy-mode = "rgmii-id"; phy-supply = <®_ethphy>; - pinctrl-names = "default", "sleep"; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; - pinctrl-1 = <&pinctrl_eqos_sleep>; mdio { compatible = "snps,dwmac-mdio"; @@ -740,26 +738,6 @@ >; }; - pinctrl_eqos_sleep: eqossleepgrp { - fsl,pins = < - MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 - MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 - MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 - MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 - MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 - MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 - MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 - MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 - MX8MP_IOMUXC_ENET_TD0__GPIO1_IO21 0x1f - MX8MP_IOMUXC_ENET_TD1__GPIO1_IO20 0x1f - MX8MP_IOMUXC_ENET_TD2__GPIO1_IO19 0x1f - MX8MP_IOMUXC_ENET_TD3__GPIO1_IO18 0x1f - MX8MP_IOMUXC_ENET_TX_CTL__GPIO1_IO22 0x1f - MX8MP_IOMUXC_ENET_TXC__GPIO1_IO23 0x1f - MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x184 - >; - }; - /* Connection Carrier Board PHY ETH_2 */ pinctrl_fec: fecgrp { fsl,pins = < |