diff options
| author | Oleksandr Suvorov <oleksandr.suvorov@toradex.com> | 2021-01-14 17:50:10 +0200 |
|---|---|---|
| committer | Oleksandr Suvorov <oleksandr.suvorov@toradex.com> | 2021-01-14 19:49:41 +0200 |
| commit | d2b28f0badb360035b48f05870ee1cec49bdfc57 (patch) | |
| tree | 84f1665f331f4b2f574776df8f5efa19aa181ec3 /arch/arm64 | |
| parent | 42beb615e362baa37da64e6284fe5a5c9390fa60 (diff) | |
arm64: dts: colibri-imx8x: add second spidev device
Colibri Aster board supports two spidev devices. Add 2nd one.
Related-to: ELB-2532
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts | 12 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi | 9 |
2 files changed, 19 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts index 06eb4f9e929d..a80825009ad2 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts @@ -24,6 +24,18 @@ pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog2>; }; +&lpspi2 { + fsl,spi-num-chipselects = <2>; + cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW + &lsio_gpio5 2 GPIO_ACTIVE_LOW>; + + spidev1: spidev@1 { + compatible = "toradex,evalspi"; + reg = <1>; + spi-max-frequency = <10000000>; + }; +}; + /* Colibri UART_B */ &lpuart0 { status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi index 6ae38c7cc1f6..20a417a6ac53 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi @@ -452,7 +452,7 @@ &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_hog2>, - <&pinctrl_ext_io0>; + <&pinctrl_ext_io0>, <&pinctrl_lpspi2_cs2>; colibri-imx8qxp { /* Colibri Analogue Inputs */ @@ -570,7 +570,6 @@ pinctrl_hog1: hog1grp { fsl,pins = < - IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020 /* SODIMM 65 */ IMX8QXP_CSI_D07_CI_PI_D09 0x61 /* SODIMM 65 */ IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x20 /* SODIMM 69 */ IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20 /* SODIMM 79 */ @@ -918,6 +917,12 @@ >; }; + pinctrl_lpspi2_cs2: lpspi2-cs2 { + fsl,pins = < + IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x21 /* SODIMM 65 */ + >; + }; + pinctrl_wifi: wifigrp { fsl,pins = < IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 |