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authorDavide Rizzo <davide@elpa.it>2008-05-03 07:53:14 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-05-07 21:44:43 +0100
commitbdd0f5f06e7647b545bec3ead2fa2a5fcdf0f0f9 (patch)
tree9aac8e303a7990efaf5bc769cca8e44c1fcf0614 /arch/arm
parent649de51b883746d76c5fa1614dd067054c9d702a (diff)
[ARM] 4882/2: Correction for S3C2410 clkout generation
This is a correction for 2 small bugs for the Samsung S3C2410 ARM9 SoC clocks generator Signed-off-by: Davide Rizzo <davide@elpa.it> Acked-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/plat-s3c24xx/clock.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/plat-s3c24xx/clock.c b/arch/arm/plat-s3c24xx/clock.c
index d84167fb33b1..3ac8d8d781b3 100644
--- a/arch/arm/plat-s3c24xx/clock.c
+++ b/arch/arm/plat-s3c24xx/clock.c
@@ -411,7 +411,7 @@ static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
clk->parent = parent;
- if (clk == &s3c24xx_dclk0)
+ if (clk == &s3c24xx_clkout0)
mask = S3C2410_MISCCR_CLK0_MASK;
else {
source <<= 4;
@@ -437,7 +437,7 @@ struct clk s3c24xx_dclk0 = {
struct clk s3c24xx_dclk1 = {
.name = "dclk1",
.id = -1,
- .ctrlbit = S3C2410_DCLKCON_DCLK0EN,
+ .ctrlbit = S3C2410_DCLKCON_DCLK1EN,
.enable = s3c24xx_dclk_enable,
.set_parent = s3c24xx_dclk_setparent,
.set_rate = s3c24xx_set_dclk_rate,