diff options
| author | Alex Frid <afrid@nvidia.com> | 2011-01-27 18:12:54 -0800 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:42:16 -0800 |
| commit | 1f871e1b10d664cfac6d65fb09b8d35f7ddc839d (patch) | |
| tree | 412802ede3a88df87730ff5325359ad4c8fd33f4 /arch/arm | |
| parent | 18e8afc5f9df7840300dc2d4870c000bd93cb64e (diff) | |
ARM: tegra: clock Increased 3D/2D Tegra3 clock limits
Original-Change-Id: Ic930ffaf2d441466bc03be0b8f97582dc750f3d7
Reviewed-on: http://git-master/r/17372
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Andrew Howe <ahowe@nvidia.com>
Tested-by: Andrew Howe <ahowe@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I9cebd7e83cdc28be5c4f7c458e71f5376b6eb84a
Rebase-Id: R5bf9f4fc77fee2b2ac5d490d606ac13c6f24c620
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_clocks.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index 0355565960ad..df3e176214ab 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -2847,9 +2847,9 @@ struct clk tegra_list_clks[] = { PERIPH_CLK("uartc", "uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART), PERIPH_CLK("uartd", "uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART), PERIPH_CLK("uarte", "uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART), - PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */ - PERIPH_CLK("3d2", "3d2", NULL, 98, 0x3b0, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */ - PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */ + PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 356000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */ + PERIPH_CLK("3d2", "3d2", NULL, 98, 0x3b0, 356000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */ + PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 356000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */ PERIPH_CLK_EX("vi", "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71, &tegra_vi_clk_ops), /* scales with voltage and process_id */ PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */ PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */ |