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authorJeff Ohlstein <johlstei@codeaurora.org>2011-04-07 17:41:09 -0700
committerArnd Bergmann <arnd@arndb.de>2011-07-21 16:43:03 +0200
commit41ff445cdb8b3d618425f8a16e2b873046bbe536 (patch)
tree60a660c1f1924b23185f67b21869b964f57e164a /arch/arm
parent620917de59eeb934b9f8cf35cc2d95c1ac8ed0fc (diff)
ARM: msm: platsmp: determine number of CPU cores at boot time
Previously we just assumed there were CONFIG_NR_CPUS cpus present in the system. Instead, figure out the number of cpus from the MIDR register. Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org> [arnd: clarified patch title] Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-msm/platsmp.c11
1 files changed, 9 insertions, 2 deletions
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index 2034098cf015..5ba77d00361c 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -18,6 +18,7 @@
#include <asm/hardware/gic.h>
#include <asm/cacheflush.h>
+#include <asm/cputype.h>
#include <asm/mach-types.h>
#include <mach/msm_iomap.h>
@@ -40,6 +41,12 @@ volatile int pen_release = -1;
static DEFINE_SPINLOCK(boot_lock);
+static inline int get_core_count(void)
+{
+ /* 1 + the PART[1:0] field of MIDR */
+ return ((read_cpuid_id() >> 4) & 3) + 1;
+}
+
void __cpuinit platform_secondary_init(unsigned int cpu)
{
/* Configure edge-triggered PPIs */
@@ -147,9 +154,9 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
*/
void __init smp_init_cpus(void)
{
- unsigned int i;
+ unsigned int i, ncores = get_core_count();
- for (i = 0; i < NR_CPUS; i++)
+ for (i = 0; i < ncores; i++)
set_cpu_possible(i, true);
set_smp_cross_call(gic_raise_softirq);