diff options
| author | Rakesh Bodla <rbodla@nvidia.com> | 2011-06-28 11:40:48 +0530 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:47:13 -0800 |
| commit | 10c5b4ab503ca1ef440e94d46f4b549dd9e649a8 (patch) | |
| tree | 4d8052a3e8fa8a6a99ee0d306ed2c59144c81318 /arch/arm | |
| parent | fe1f889383bb4ecd8eb18a830b63e613dd2acdb8 (diff) | |
arm: tegra: usb_phy: update BIAS and XCVR registers
Modifing the UTMIP_BIAS_CFG0 and UTMIP_XCVR_CFG0
register settings to pass HS eye-diagram and receiver
sensitivity tests.
Bug 842700
Original-Change-Id: I4660fc3bd4d620408b52ed274232762fe50abee2
Reviewed-on: http://git-master/r/38510
Tested-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com>
Tested-by: Gerrit_Virtual_Submit
Rebase-Id: R3dec3d6e8699a6202482946ea49d0d98fe2cf48c
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-tegra/usb_phy.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c index f2066a4f423c..3dc23f3a7329 100644 --- a/arch/arm/mach-tegra/usb_phy.c +++ b/arch/arm/mach-tegra/usb_phy.c @@ -257,6 +257,9 @@ #define UTMIP_BIAS_CFG0 0x80c #define UTMIP_OTGPD (1 << 11) #define UTMIP_BIASPD (1 << 10) +#define UTMIP_HSSQUELCH_LEVEL(x) (((x) & 0x2) << 0) +#define UTMIP_HSDISCON_LEVEL(x) (((x) & 0x2) << 2) +#define UTMIP_HSDISCON_LEVEL_MSB (1 << 24) #define UTMIP_HSRX_CFG0 0x810 #define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10) @@ -561,6 +564,10 @@ static int utmip_pad_power_on(struct tegra_usb_phy *phy) if (utmip_pad_count++ == 0) { val = readl(base + UTMIP_BIAS_CFG0); val &= ~(UTMIP_OTGPD | UTMIP_BIASPD); +#ifndef CONFIG_ARCH_TEGRA_2x_SOC + val |= UTMIP_HSSQUELCH_LEVEL(0x2) | UTMIP_HSDISCON_LEVEL(0x2) | + UTMIP_HSDISCON_LEVEL_MSB; +#endif writel(val, base + UTMIP_BIAS_CFG0); } @@ -588,6 +595,10 @@ static int utmip_pad_power_off(struct tegra_usb_phy *phy, bool is_dpd) if (--utmip_pad_count == 0 && is_dpd) { val = readl(base + UTMIP_BIAS_CFG0); val |= UTMIP_OTGPD | UTMIP_BIASPD; +#ifndef CONFIG_ARCH_TEGRA_2x_SOC + val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | UTMIP_HSDISCON_LEVEL(~0) | + UTMIP_HSDISCON_LEVEL_MSB); +#endif writel(val, base + UTMIP_BIAS_CFG0); } @@ -789,6 +800,10 @@ static int utmi_phy_power_on(struct tegra_usb_phy *phy, bool is_dpd) val |= UTMIP_XCVR_SETUP(config->xcvr_setup); val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew); val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew); +#ifndef CONFIG_ARCH_TEGRA_2x_SOC + if (phy->instance == 0) + val |= UTMIP_XCVR_HSSLEW_MSB(0x8); +#endif writel(val, base + UTMIP_XCVR_CFG0); val = readl(base + UTMIP_XCVR_CFG1); |