ARM: tegra: power: Set minimum LP2 target residency

Added board level tuning parameter to specify minimum LP2 residency
time (previous policy allows down to zero residency targets limited
only by LP2 exit latency).

Original-Change-Id: I4ae7d458fba78f35a40f138cf9489bf938715b22
Reviewed-on: http://git-master/r/28162
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Original-Change-Id: I38e798ca6d242d136ea2353d90cc961de14f25b6

Rebase-Id: Rcf9efce3dd037b0a7ca13a9c342f884fac38d654

3 files changed, 20 insertions, 1 deletions

diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c
index 4f975fb72be1..465b8aa1fbc1 100644
--- a/arch/arm/mach-tegra/cpuidle.c
+++ b/arch/arm/mach-tegra/cpuidle.c
@@ -3,7 +3,7 @@
  *
  * CPU idle driver for Tegra CPUs
  *
- * Copyright (c) 2010, NVIDIA Corporation.
+ * Copyright (c) 2010-2011, NVIDIA Corporation.
  * Copyright (c) 2011 Google, Inc.
  * Author: Colin Cross <ccross@android.com>
  *         Gary King <gking@nvidia.com>
@@ -58,6 +58,8 @@ static struct {
 	unsigned int last_lp2_int_count[NR_IRQS];
 } idle_stats;
 
+static unsigned int tegra_lp2_min_residency;
+
 struct cpuidle_driver tegra_idle = {
 	.name = "tegra_idle",
 	.owner = THIS_MODULE,
@@ -115,6 +117,8 @@ static int tegra_idle_enter_lp2(struct cpuidle_device *dev,
 	hrtimer_peek_ahead_timers();
 
 	smp_rmb();
+	if (state->target_residency < tegra_lp2_min_residency)
+		state->target_residency = tegra_lp2_min_residency;
 
 	idle_stats.cpu_wants_lp2_time[dev->cpu] += us;
 
@@ -143,6 +147,8 @@ static int tegra_idle_enter(unsigned int cpu)
 	dev->state_count = 0;
 	dev->cpu = cpu;
 
+	tegra_lp2_min_residency = tegra_cpu_lp2_min_residency();
+
 	state = &dev->states[0];
 	snprintf(state->name, CPUIDLE_NAME_LEN, "LP3");
 	snprintf(state->desc, CPUIDLE_DESC_LEN, "CPU flow-controlled");
@@ -161,6 +167,8 @@ static int tegra_idle_enter(unsigned int cpu)
 
 	state->target_residency = tegra_cpu_power_off_time() +
 		tegra_cpu_power_good_time();
+	if (state->target_residency < tegra_lp2_min_residency)
+		state->target_residency = tegra_lp2_min_residency;
 	state->power_usage = 0;
 	state->flags = CPUIDLE_FLAG_TIME_VALID;
 	state->enter = tegra_idle_enter_lp2;
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index fb1337f04443..3ce2e682feb4 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -235,6 +235,14 @@ unsigned long tegra_cpu_power_off_time(void)
 	return pdata->cpu_off_timer;
 }
 
+unsigned long tegra_cpu_lp2_min_residency(void)
+{
+	if (WARN_ON_ONCE(!pdata))
+		return 2000;
+
+	return pdata->cpu_lp2_min_residency;
+}
+
 /* ensures that sufficient time is passed for a register write to
  * serialize into the 32KHz domain */
 static void pmc_32kwritel(u32 val, unsigned long offs)
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h
index b19209292a04..756fd4da3b61 100644
--- a/arch/arm/mach-tegra/pm.h
+++ b/arch/arm/mach-tegra/pm.h
@@ -2,6 +2,7 @@
  * arch/arm/mach-tegra/include/mach/suspend.h
  *
  * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2011 NVIDIA Corporation
  *
  * Author:
  *	Colin Cross <ccross@google.com>
@@ -39,10 +40,12 @@ struct tegra_suspend_platform_data {
 	bool corereq_high;         /* Core power request active-high */
 	bool sysclkreq_high;       /* System clock request is active-high */
 	enum tegra_suspend_mode suspend_mode;
+	unsigned long cpu_lp2_min_residency; /* Min LP2 state residency in us */
 };
 
 unsigned long tegra_cpu_power_good_time(void);
 unsigned long tegra_cpu_power_off_time(void);
+unsigned long tegra_cpu_lp2_min_residency(void);
 
 #define TEGRA_POWER_SDRAM_SELFREFRESH	0x400	/* SDRAM is in self-refresh */