ARM: tegra3: dvfs: Added DVFS entries

Added dvfs entries for automotive skus

Bug 883565, 882186

Change-Id: I6186b682fa82e24c3062bcbf5c2e5580fdf80562
Signed-off-by: Mohit Kataria<mkataria@nvidia.com>
Reviewed-on: http://git-master/r/70292
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

2 files changed, 135 insertions, 75 deletions

diff --git a/arch/arm/mach-tegra/tegra3_dvfs.c b/arch/arm/mach-tegra/tegra3_dvfs.c
index 4ec22d1b9485..f1f2e8fbf007 100644
--- a/arch/arm/mach-tegra/tegra3_dvfs.c
+++ b/arch/arm/mach-tegra/tegra3_dvfs.c
@@ -32,7 +32,7 @@ static bool tegra_dvfs_cpu_disabled;
 static bool tegra_dvfs_core_disabled;
 
 static const int cpu_millivolts[MAX_DVFS_FREQS] =
-	{800, 825, 850, 875, 900, 925, 950, 975, 1000, 1025, 1050, 1075, 1100, 1125, 1150, 1200, 1237};
+	{800, 825, 850, 875, 900, 912, 925, 950, 975, 1000, 1025, 1050, 1075, 1100, 1125, 1150, 1200, 1237};
 
 static const int core_millivolts[MAX_DVFS_FREQS] =
 	{1000, 1050, 1100, 1150, 1200, 1250, 1300};
@@ -133,47 +133,51 @@ static struct dvfs_relationship tegra3_dvfs_relationships[] = {
 	}
 
 static struct dvfs cpu_dvfs_table[] = {
-	/* Cpu voltages (mV):	     800, 825, 850, 875,  900,  925,  950,  975, 1000, 1025, 1050, 1075, 1100, 1125, 1150, 1200, 1237 */
-	CPU_DVFS("cpu_g", 0, 0, MHZ,   1,   1, 684, 684,  817,  817,  817, 1026, 1102, 1149, 1187, 1225, 1282, 1300),
-	CPU_DVFS("cpu_g", 0, 1, MHZ,   1,   1, 807, 807,  948,  948,  948, 1117, 1171, 1206, 1300),
-	CPU_DVFS("cpu_g", 0, 2, MHZ,   1,   1, 883, 883, 1039, 1039, 1039, 1178, 1206, 1300),
-	CPU_DVFS("cpu_g", 0, 3, MHZ,   1,   1, 931, 931, 1102, 1102, 1102, 1216, 1300),
-
-	CPU_DVFS("cpu_g", 1, 0, MHZ,   1,   1, 550, 550,  680,  680,  680,  820,  970, 1040, 1080, 1150, 1200, 1280, 1300),
-	CPU_DVFS("cpu_g", 1, 1, MHZ,   1,   1, 650, 650,  820,  820,  820, 1000, 1060, 1100, 1200, 1300),
-	CPU_DVFS("cpu_g", 1, 2, MHZ,   1,   1, 720, 720,  880,  880,  880, 1090, 1180, 1200, 1300),
-	CPU_DVFS("cpu_g", 1, 3, MHZ,   1,   1, 800, 800, 1000, 1000, 1000, 1180, 1230, 1300),
-
-	CPU_DVFS("cpu_g", 2, 1, MHZ,   1,   1, 650, 650,  820,  820,  820, 1000, 1060, 1100, 1200, 1250, 1300, 1330, 1400),
-	CPU_DVFS("cpu_g", 2, 2, MHZ,   1,   1, 720, 720,  880,  880,  880, 1090, 1180, 1200, 1300, 1310, 1350, 1400),
-	CPU_DVFS("cpu_g", 2, 3, MHZ,   1,   1, 800, 800, 1000, 1000, 1000, 1180, 1230, 1300, 1320, 1350, 1400),
-
-	CPU_DVFS("cpu_g", 3, 1, MHZ,   1,   1, 650, 650,  820,  820,  820, 1000, 1060, 1100, 1200, 1250, 1300, 1330, 1400),
-	CPU_DVFS("cpu_g", 3, 2, MHZ,   1,   1, 720, 720,  880,  880,  880, 1090, 1180, 1200, 1300, 1310, 1350, 1400),
-	CPU_DVFS("cpu_g", 3, 3, MHZ,   1,   1, 800, 800, 1000, 1000, 1000, 1180, 1230, 1300, 1320, 1350, 1400),
-
-	CPU_DVFS("cpu_g", 4, 0, MHZ,   1,   1, 550, 550,  680,  680,  680,  820,  970, 1040, 1080, 1150, 1200, 1280, 1350, 1400, 1500),
-	CPU_DVFS("cpu_g", 4, 1, MHZ,   1,   1, 650, 650,  820,  820,  820, 1000, 1060, 1100, 1200, 1250, 1300, 1360, 1400, 1500),
-	CPU_DVFS("cpu_g", 4, 2, MHZ,   1,   1, 720, 720,  880,  880,  880, 1090, 1180, 1200, 1300, 1310, 1380, 1400, 1500),
-	CPU_DVFS("cpu_g", 4, 3, MHZ,   1,   1, 800, 800, 1000, 1000, 1000, 1180, 1230, 1300, 1330, 1380, 1400, 1500),
-
-	CPU_DVFS("cpu_g", 5, 3, MHZ,   1,   1, 800, 800, 1000, 1000, 1000, 1180, 1230, 1300, 1330, 1380, 1400, 1470, 1500, 1540, 1700),
-	CPU_DVFS("cpu_g", 5, 4, MHZ,   1,   1, 840, 840, 1000, 1000, 1000, 1200, 1280, 1330, 1380, 1400, 1480, 1500, 1520, 1700),
-
-	CPU_DVFS("cpu_g", 6, 3, MHZ,   1,   1, 800, 800, 1000, 1000, 1000, 1180, 1230, 1300, 1330, 1380, 1400, 1470, 1500, 1540, 1700),
-	CPU_DVFS("cpu_g", 6, 4, MHZ,   1,   1, 840, 840, 1000, 1000, 1000, 1200, 1280, 1330, 1380, 1400, 1480, 1500, 1520, 1700),
-
-	CPU_DVFS("cpu_g", 7, 0, MHZ,   1,   1, 550, 550,  680,  680,  680,  820,  970, 1040, 1080, 1150, 1200, 1280, 1300),
-	CPU_DVFS("cpu_g", 7, 1, MHZ,   1,   1, 650, 650,  820,  820,  820, 1000, 1060, 1100, 1200, 1300),
-	CPU_DVFS("cpu_g", 7, 2, MHZ,   1,   1, 720, 720,  880,  880,  880, 1090, 1180, 1200, 1300),
-	CPU_DVFS("cpu_g", 7, 3, MHZ,   1,   1, 800, 800, 1000, 1000, 1000, 1180, 1200, 1300),
-	CPU_DVFS("cpu_g", 7, 4, MHZ,   1,   1, 840, 840, 1000, 1000, 1000, 1200, 1300),
-
-	CPU_DVFS("cpu_g", 8, 0, MHZ,   1,   1, 550, 550,  680,  680,  680,  820,  970, 1040, 1080, 1150, 1200, 1280, 1300),
-	CPU_DVFS("cpu_g", 8, 1, MHZ,   1,   1, 650, 650,  820,  820,  820, 1000, 1060, 1100, 1200, 1300),
-	CPU_DVFS("cpu_g", 8, 2, MHZ,   1,   1, 720, 720,  880,  880,  880, 1090, 1180, 1200, 1300),
-	CPU_DVFS("cpu_g", 8, 3, MHZ,   1,   1, 800, 800, 1000, 1000, 1000, 1180, 1200, 1300),
-	CPU_DVFS("cpu_g", 8, 4, MHZ,   1,   1, 840, 840, 1000, 1000, 1000, 1200, 1300),
+	/* Cpu voltages (mV):	     800, 825, 850, 875,  900,  912,  925,  950,  975, 1000, 1025, 1050, 1075, 1100, 1125, 1150, 1200, 1237 */
+	CPU_DVFS("cpu_g",  0, 0, MHZ,   1,   1, 684, 684,  817,  817,  817,  817, 1026, 1102, 1149, 1187, 1225, 1282, 1300),
+	CPU_DVFS("cpu_g",  0, 1, MHZ,   1,   1, 807, 807,  948,  948,  948,  948, 1117, 1171, 1206, 1300),
+	CPU_DVFS("cpu_g",  0, 2, MHZ,   1,   1, 883, 883, 1039, 1039, 1039, 1039, 1178, 1206, 1300),
+	CPU_DVFS("cpu_g",  0, 3, MHZ,   1,   1, 931, 931, 1102, 1102, 1102, 1102, 1216, 1300),
+
+	CPU_DVFS("cpu_g",  1, 0, MHZ,   1,   1, 550, 550,  680,  680,  680,  680,  820,  970, 1040, 1080, 1150, 1200, 1280, 1300),
+	CPU_DVFS("cpu_g",  1, 1, MHZ,   1,   1, 650, 650,  820,  820,  820,  820, 1000, 1060, 1100, 1200, 1300),
+	CPU_DVFS("cpu_g",  1, 2, MHZ,   1,   1, 720, 720,  880,  880,  880,  880, 1090, 1180, 1200, 1300),
+	CPU_DVFS("cpu_g",  1, 3, MHZ,   1,   1, 800, 800, 1000, 1000, 1000, 1000, 1180, 1230, 1300),
+
+	CPU_DVFS("cpu_g",  2, 1, MHZ,   1,   1, 650, 650,  820,  820,  820,  820, 1000, 1060, 1100, 1200, 1250, 1300, 1330, 1400),
+	CPU_DVFS("cpu_g",  2, 2, MHZ,   1,   1, 720, 720,  880,  880,  880,  880, 1090, 1180, 1200, 1300, 1310, 1350, 1400),
+	CPU_DVFS("cpu_g",  2, 3, MHZ,   1,   1, 800, 800, 1000, 1000, 1000, 1000, 1180, 1230, 1300, 1320, 1350, 1400),
+
+	CPU_DVFS("cpu_g",  3, 1, MHZ,   1,   1, 650, 650,  820,  820,  820,  820, 1000, 1060, 1100, 1200, 1250, 1300, 1330, 1400),
+	CPU_DVFS("cpu_g",  3, 2, MHZ,   1,   1, 720, 720,  880,  880,  880,  880, 1090, 1180, 1200, 1300, 1310, 1350, 1400),
+	CPU_DVFS("cpu_g",  3, 3, MHZ,   1,   1, 800, 800, 1000, 1000, 1000, 1000, 1180, 1230, 1300, 1320, 1350, 1400),
+
+	CPU_DVFS("cpu_g",  4, 0, MHZ,   1,   1, 550, 550,  680,  680,  680,  680,  820,  970, 1040, 1080, 1150, 1200, 1280, 1350, 1400, 1500),
+	CPU_DVFS("cpu_g",  4, 1, MHZ,   1,   1, 650, 650,  820,  820,  820,  820, 1000, 1060, 1100, 1200, 1250, 1300, 1360, 1400, 1500),
+	CPU_DVFS("cpu_g",  4, 2, MHZ,   1,   1, 720, 720,  880,  880,  880,  880, 1090, 1180, 1200, 1300, 1310, 1380, 1400, 1500),
+	CPU_DVFS("cpu_g",  4, 3, MHZ,   1,   1, 800, 800, 1000, 1000, 1000, 1000, 1180, 1230, 1300, 1330, 1380, 1400, 1500),
+
+	CPU_DVFS("cpu_g",  5, 3, MHZ,   1,   1, 800, 800, 1000, 1000, 1000, 1000, 1180, 1230, 1300, 1330, 1380, 1400, 1470, 1500, 1540, 1700),
+	CPU_DVFS("cpu_g",  5, 4, MHZ,   1,   1, 840, 840, 1000, 1000, 1000, 1000, 1200, 1280, 1330, 1380, 1400, 1480, 1500, 1520, 1700),
+
+	CPU_DVFS("cpu_g",  6, 3, MHZ,   1,   1, 800, 800, 1000, 1000, 1000, 1000, 1180, 1230, 1300, 1330, 1380, 1400, 1470, 1500, 1540, 1700),
+	CPU_DVFS("cpu_g",  6, 4, MHZ,   1,   1, 840, 840, 1000, 1000, 1000, 1000, 1200, 1280, 1330, 1380, 1400, 1480, 1500, 1520, 1700),
+
+	CPU_DVFS("cpu_g",  7, 0, MHZ,   1,   1, 550, 550,  680,  680,  680,  680,  820,  970, 1040, 1080, 1150, 1200, 1280, 1300),
+	CPU_DVFS("cpu_g",  7, 1, MHZ,   1,   1, 650, 650,  820,  820,  820,  820, 1000, 1060, 1100, 1200, 1300),
+	CPU_DVFS("cpu_g",  7, 2, MHZ,   1,   1, 720, 720,  880,  880,  880,  880, 1090, 1180, 1200, 1300),
+	CPU_DVFS("cpu_g",  7, 3, MHZ,   1,   1, 800, 800, 1000, 1000, 1000, 1000, 1180, 1200, 1300),
+	CPU_DVFS("cpu_g",  7, 4, MHZ,   1,   1, 840, 840, 1000, 1000, 1000, 1000, 1200, 1300),
+
+	CPU_DVFS("cpu_g",  8, 0, MHZ,   1,   1, 550, 550,  680,  680,  680,  680,  820,  970, 1040, 1080, 1150, 1200, 1280, 1300),
+	CPU_DVFS("cpu_g",  8, 1, MHZ,   1,   1, 650, 650,  820,  820,  820,  820, 1000, 1060, 1100, 1200, 1300),
+	CPU_DVFS("cpu_g",  8, 2, MHZ,   1,   1, 720, 720,  880,  880,  880,  880, 1090, 1180, 1200, 1300),
+	CPU_DVFS("cpu_g",  8, 3, MHZ,   1,   1, 800, 800, 1000, 1000, 1000, 1000, 1180, 1200, 1300),
+	CPU_DVFS("cpu_g",  8, 4, MHZ,   1,   1, 840, 840, 1000, 1000, 1000, 1000, 1200, 1300),
+
+	CPU_DVFS("cpu_g",  9, -1, MHZ,  1,   1,   1,   1,    1,  900,  900,  900,  900,  900,  900,  900,  900,  900,  900,  900),
+	CPU_DVFS("cpu_g", 10, -1, MHZ,  1,   1, 900, 900,  900,  900,  900,  900,  900,  900,  900,  900,  900,  900,  900,  900),
+	CPU_DVFS("cpu_g", 11, -1, MHZ,  1,   1, 600, 600,  600,  600,  600,  600,  600,  600,  600,  600,  600,  600,  600,  600),
 
 	/*
 	 * "Safe entry" to be used when no match for chip speedo, process
@@ -200,18 +204,22 @@ static struct dvfs core_dvfs_table[] = {
 	CORE_DVFS("cpu_lp", 0, 1, KHZ,   294000, 342000, 427000, 475000,  500000,  500000,  500000),
 	CORE_DVFS("cpu_lp", 1, 1, KHZ,   294000, 342000, 427000, 475000,  500000,  500000,  500000),
 	CORE_DVFS("cpu_lp", 2, 1, KHZ,   295000, 370000, 428000, 475000,  513000,  579000,  620000),
+	CORE_DVFS("cpu_lp", 3, 1, KHZ,        1,      1,      1,      1,       1,  450000,  450000),
 
 	CORE_DVFS("emc",    0, 1, KHZ,   266500, 266500, 266500, 266500,  533000,  533000,  533000),
 	CORE_DVFS("emc",    1, 1, KHZ,   408000, 408000, 408000, 408000,  667000,  667000,  667000),
 	CORE_DVFS("emc",    2, 1, KHZ,   408000, 408000, 408000, 408000,  667000,  667000,  800000),
+	CORE_DVFS("emc",    3, 1, KHZ,        1,      1,      1,      1,       1,  625000,  625000),
 
 	CORE_DVFS("sbus",   0, 1, KHZ,   136000, 164000, 191000, 216000,  216000,  216000,  216000),
 	CORE_DVFS("sbus",   1, 1, KHZ,   205000, 205000, 227000, 227000,  267000,  267000,  267000),
 	CORE_DVFS("sbus",   2, 1, KHZ,   205000, 205000, 227000, 227000,  267000,  334000,  334000),
+	CORE_DVFS("sbus",   3, 1, KHZ,        1,      1,      1,      1,       1,  216000,  216000),
 
 	CORE_DVFS("vi",     0, 1, KHZ,   216000, 285000, 300000, 300000,  300000,  300000,  300000),
 	CORE_DVFS("vi",     1, 1, KHZ,   216000, 267000, 300000, 371000,  409000,  409000,  409000),
 	CORE_DVFS("vi",     2, 1, KHZ,   219000, 267000, 300000, 371000,  409000,  425000,  425000),
+	CORE_DVFS("vi",     3, 1, KHZ,        1,      1,      1,      1,       1,  300000,  300000),
 
 	CORE_DVFS("vde",    0, 1, KHZ,   228000, 275000, 332000, 380000,  416000,  416000,  416000),
 	CORE_DVFS("mpe",    0, 1, KHZ,   234000, 285000, 332000, 380000,  416000,  416000,  416000),
@@ -237,36 +245,55 @@ static struct dvfs core_dvfs_table[] = {
 	CORE_DVFS("3d2",    2, 1, KHZ,   247000, 304000, 361000, 408000,  446000,  484000,  520000),
 	CORE_DVFS("se",     2, 1, KHZ,   267000, 304000, 361000, 408000,  446000,  484000,  520000),
 
-	CORE_DVFS("host1x",-1, 1, KHZ,   152000, 188000, 222000, 254000,  267000,  267000,  267000),
+	CORE_DVFS("vde",    3, 1, KHZ,        1,      1,      1,      1,       1,  484000,  484000),
+	CORE_DVFS("mpe",    3, 1, KHZ,        1,      1,      1,      1,       1,  484000,  484000),
+	CORE_DVFS("2d",     3, 1, KHZ,        1,      1,      1,      1,       1,  484000,  484000),
+	CORE_DVFS("epp",    3, 1, KHZ,        1,      1,      1,      1,       1,  484000,  484000),
+	CORE_DVFS("3d",     3, 1, KHZ,        1,      1,      1,      1,       1,  484000,  484000),
+	CORE_DVFS("3d2",    3, 1, KHZ,        1,      1,      1,      1,       1,  484000,  484000),
+	CORE_DVFS("se",     3, 1, KHZ,        1,      1,      1,      1,       1,  650000,  650000),
+
+	CORE_DVFS("host1x", 0, 1, KHZ,   152000, 188000, 222000, 254000,  267000,  267000,  267000),
+	CORE_DVFS("host1x", 1, 1, KHZ,   152000, 188000, 222000, 254000,  267000,  267000,  267000),
+	CORE_DVFS("host1x", 2, 1, KHZ,   152000, 188000, 222000, 254000,  267000,  267000,  267000),
+	CORE_DVFS("host1x", 3, 1, KHZ,        1,      1,      1,      1,       1,  300000,  300000),
 
 	CORE_DVFS("cbus",   0, 1, KHZ,   228000, 275000, 332000, 380000,  416000,  416000,  416000),
 	CORE_DVFS("cbus",   1, 1, KHZ,   228000, 275000, 332000, 380000,  416000,  416000,  416000),
 	CORE_DVFS("cbus",   2, 1, KHZ,   247000, 304000, 352000, 400000,  437000,  484000,  520000),
+	CORE_DVFS("cbus",   3, 1, KHZ,   484000, 484000, 484000, 484000,  484000,  484000,  484000),
 
-	CORE_DVFS("pll_c",  -1, 1, KHZ,   667000, 667000, 800000, 800000, 1066000, 1066000, 1066000),
-	CORE_DVFS("pll_m",  -1, 1, KHZ,   667000, 667000, 800000, 800000, 1066000, 1066000, 1066000),
+	CORE_DVFS("pll_c",  -1, 1, KHZ,  667000, 667000, 800000, 800000, 1066000, 1066000, 1066000),
+	CORE_DVFS("pll_m",  -1, 1, KHZ,  667000, 667000, 800000, 800000, 1066000, 1066000, 1066000),
 
 	/* Core voltages (mV):		   1000,   1050,   1100,   1150,    1200,   1250,    1300 */
 	/* Clock limits for I/O peripherals */
-	CORE_DVFS("mipi",   0, 1, KHZ,        1,      1,      1,      1,      1,       1,       1),
-	CORE_DVFS("mipi",   1, 1, KHZ,        1,      1,      1,      1,  60000,   60000,   60000),
-	CORE_DVFS("mipi",   2, 1, KHZ,        1,      1,      1,      1,  60000,   60000,   60000),
-
-	CORE_DVFS("fuse_burn", -1, 1, KHZ,    1,      1,      1,  26000,  26000,   26000,   26000),
-	CORE_DVFS("sdmmc1",-1, 1, KHZ,   104000, 104000, 104000, 104000, 208000,  208000,  208000),
-	CORE_DVFS("sdmmc3",-1, 1, KHZ,   104000, 104000, 104000, 104000, 208000,  208000,  208000),
-	CORE_DVFS("ndflash", -1, 1, KHZ, 120000, 120000, 120000, 200000, 200000,  200000,  200000),
-	CORE_DVFS("nor",   -1, 1, KHZ,   115000, 130000, 130000, 133000, 133000,  133000,  133000),
-	CORE_DVFS("sbc1",  -1, 1, KHZ,    40000,  60000,  60000,  60000, 100000,  100000,  100000),
-	CORE_DVFS("sbc2",  -1, 1, KHZ,    40000,  60000,  60000,  60000, 100000,  100000,  100000),
-	CORE_DVFS("sbc3",  -1, 1, KHZ,    40000,  60000,  60000,  60000, 100000,  100000,  100000),
-	CORE_DVFS("sbc4",  -1, 1, KHZ,    40000,  60000,  60000,  60000, 100000,  100000,  100000),
-	CORE_DVFS("sbc5",  -1, 1, KHZ,    40000,  60000,  60000,  60000, 100000,  100000,  100000),
-	CORE_DVFS("sbc6",  -1, 1, KHZ,    40000,  60000,  60000,  60000, 100000,  100000,  100000),
-	CORE_DVFS("tvo",   -1, 1, KHZ,        1, 297000, 297000, 297000, 297000,  297000,  297000),
-	CORE_DVFS("cve",   -1, 1, KHZ,        1, 297000, 297000, 297000, 297000,  297000,  297000),
-	CORE_DVFS("dsia",  -1, 1, KHZ,   275000, 275000, 275000, 275000, 275000,  275000,  275000),
-	CORE_DVFS("dsib",  -1, 1, KHZ,   275000, 275000, 275000, 275000, 275000,  275000,  275000),
+	CORE_DVFS("mipi",   0, 1, KHZ,        1,      1,      1,      1,      1,       1,        1),
+	CORE_DVFS("mipi",   1, 1, KHZ,        1,      1,      1,      1,  60000,   60000,    60000),
+	CORE_DVFS("mipi",   2, 1, KHZ,        1,      1,      1,      1,  60000,   60000,    60000),
+	CORE_DVFS("mipi",   3, 1, KHZ,        1,      1,      1,      1,      1,       1,        1),
+
+	CORE_DVFS("fuse_burn", -1, 1, KHZ,    1,      1,      1,  26000,  26000,   26000,    26000),
+	CORE_DVFS("sdmmc1",-1, 1, KHZ,   104000, 104000, 104000, 104000, 208000,  208000,   208000),
+	CORE_DVFS("sdmmc3",-1, 1, KHZ,   104000, 104000, 104000, 104000, 208000,  208000,   208000),
+	CORE_DVFS("ndflash", -1, 1, KHZ, 120000, 120000, 120000, 200000, 200000,  200000,   200000),
+
+	CORE_DVFS("nor",    0, 1, KHZ,   115000, 130000, 130000, 133000, 133000,  133000,   133000),
+	CORE_DVFS("nor",    1, 1, KHZ,   115000, 130000, 130000, 133000, 133000,  133000,   133000),
+	CORE_DVFS("nor",    2, 1, KHZ,   115000, 130000, 130000, 133000, 133000,  133000,   133000),
+	CORE_DVFS("nor",    3, 1, KHZ,        1,      1,      1,      1,      1,  108000,   108000),
+
+	CORE_DVFS("sbc1",  -1, 1, KHZ,    40000,  60000,  60000,  60000, 100000,  100000,   100000),
+	CORE_DVFS("sbc2",  -1, 1, KHZ,    40000,  60000,  60000,  60000, 100000,  100000,   100000),
+	CORE_DVFS("sbc3",  -1, 1, KHZ,    40000,  60000,  60000,  60000, 100000,  100000,   100000),
+	CORE_DVFS("sbc4",  -1, 1, KHZ,    40000,  60000,  60000,  60000, 100000,  100000,   100000),
+	CORE_DVFS("sbc5",  -1, 1, KHZ,    40000,  60000,  60000,  60000, 100000,  100000,   100000),
+	CORE_DVFS("sbc6",  -1, 1, KHZ,    40000,  60000,  60000,  60000, 100000,  100000,   100000),
+
+	CORE_DVFS("tvo",   -1, 1, KHZ,        1, 297000, 297000, 297000, 297000,  297000,   297000),
+	CORE_DVFS("cve",   -1, 1, KHZ,        1, 297000, 297000, 297000, 297000,  297000,   297000),
+	CORE_DVFS("dsia",  -1, 1, KHZ,   275000, 275000, 275000, 275000, 275000,  275000,   275000),
+	CORE_DVFS("dsib",  -1, 1, KHZ,   275000, 275000, 275000, 275000, 275000,  275000,   275000),
 
 	/*
 	 * The clock rate for the display controllers that determines the
@@ -274,13 +301,15 @@ static struct dvfs core_dvfs_table[] = {
 	 * to the display block.  Disable auto-dvfs on the display clocks,
 	 * and let the display driver call tegra_dvfs_set_rate manually
 	 */
-	CORE_DVFS("disp1",  0, 0, KHZ,   120000, 120000, 120000, 120000, 190000,  190000,  190000),
-	CORE_DVFS("disp1",  1, 0, KHZ,   151000, 268000, 268000, 268000, 268000,  268000,  268000),
-	CORE_DVFS("disp1",  2, 0, KHZ,   151000, 268000, 268000, 268000, 268000,  268000,  268000),
-
-	CORE_DVFS("disp2",  0, 0, KHZ,   120000, 120000, 120000, 120000, 190000,  190000,  190000),
-	CORE_DVFS("disp2",  1, 0, KHZ,   151000, 268000, 268000, 268000, 268000,  268000,  268000),
-	CORE_DVFS("disp2",  2, 0, KHZ,   151000, 268000, 268000, 268000, 268000,  268000,  268000),
+	CORE_DVFS("disp1",  0, 0, KHZ,   120000, 120000, 120000, 120000, 190000,  190000,   190000),
+	CORE_DVFS("disp1",  1, 0, KHZ,   151000, 268000, 268000, 268000, 268000,  268000,   268000),
+	CORE_DVFS("disp1",  2, 0, KHZ,   151000, 268000, 268000, 268000, 268000,  268000,   268000),
+	CORE_DVFS("disp1",  3, 0, KHZ,   120000, 120000, 120000, 120000, 190000,  190000,   190000),
+
+	CORE_DVFS("disp2",  0, 0, KHZ,   120000, 120000, 120000, 120000, 190000,  190000,   190000),
+	CORE_DVFS("disp2",  1, 0, KHZ,   151000, 268000, 268000, 268000, 268000,  268000,   268000),
+	CORE_DVFS("disp2",  2, 0, KHZ,   151000, 268000, 268000, 268000, 268000,  268000,   268000),
+	CORE_DVFS("disp2",  3, 0, KHZ,   120000, 120000, 120000, 120000, 190000,  190000,   190000),
 };
 
 
diff --git a/arch/arm/mach-tegra/tegra3_speedo.c b/arch/arm/mach-tegra/tegra3_speedo.c
index 5c37fd3f3a84..a9dfb7344b1e 100644
--- a/arch/arm/mach-tegra/tegra3_speedo.c
+++ b/arch/arm/mach-tegra/tegra3_speedo.c
@@ -26,7 +26,7 @@
 #include "fuse.h"
 
 #define CORE_PROCESS_CORNERS_NUM	1
-#define CPU_PROCESS_CORNERS_NUM		5
+#define CPU_PROCESS_CORNERS_NUM	7
 
 #define FUSE_SPEEDO_CALIB_0	0x114
 #define FUSE_PACKAGE_INFO	0X1FC
@@ -54,6 +54,10 @@ static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = {
 /* T30 'L' family */
 	{192}, /* [10]: soc_speedo_id 1: T30L */
 	{192}, /* [11]: soc_speedo_id 1: T30SL */
+
+/* T30 Automotives */
+	{185}, /* [12]: soc_speedo_id = 3 - Automotives */
+	{185}, /* [13]: soc_speedo_id = 3 - Automotives */
 };
 
 /* Maximum speedo levels for each CPU process corner */
@@ -79,6 +83,14 @@ static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = {
 /* T30 'L' family */
 	{305, 337, 359, 376, 392},	/* [10]: cpu_speedo_id 7: T30L  */
 	{305, 337, 359, 376, 392},	/* [11]: cpu_speedo_id 8: T30SL */
+
+/* T30 Automotives */
+	/* threshold_index 12: cpu_speedo_id 9 & 10
+	 * 0,1,2 values correspond to speedo_id  9
+	 * 3,4,5 values correspond to speedo_id 10
+	 */
+	{300, 311, 360, 371, 381, 415, 431},
+	{300, 311, 410, 431}, /* threshold_index 13: cpu_speedo_id = 11 */
 };
 
 /*
@@ -209,6 +221,18 @@ static void rev_sku_to_speedo_ids(int rev, int sku)
 			threshold_index = 6;
 			break;
 
+		case 0x91: /* T30AGS-Ax */
+		case 0xb0: /* T30IQS-Ax */
+		case 0xb1: /* T30MQS-Ax */
+		case 0x90: /* T30AQS-Ax */
+			soc_speedo_id = 3;
+			threshold_index = 12;
+			break;
+		case 0x93: /* T30AG-Ax */
+			cpu_speedo_id = 11;
+			soc_speedo_id = 3;
+			threshold_index = 13;
+			break;
 		case 0:    /* ENG - check package_id */
 			pr_info("Tegra3 ENG SKU: Checking package_id\n");
 			switch (package_id) {
@@ -303,7 +327,12 @@ void tegra_init_speedo_data(void)
 		core_process_id = INVALID_PROCESS_ID;
 		soc_speedo_id = 1;
 	}
-
+	if (threshold_index == 12 && cpu_process_id != INVALID_PROCESS_ID) {
+		if (cpu_process_id <= 2)
+			cpu_speedo_id = 9;
+		else if (cpu_process_id >= 3 && cpu_process_id < 6)
+			cpu_speedo_id = 10;
+	}
 	pr_info("Tegra3: CPU Speedo ID %d, Soc Speedo ID %d",
 		 cpu_speedo_id, soc_speedo_id);
 }
@@ -347,8 +376,8 @@ int tegra_package_id(void)
  * latter is resolved by the dvfs code)
  */
 static const int cpu_speedo_nominal_millivolts[] =
-/* speedo_id 0,    1,    2,    3,    4,    5,    6,    7,    8 */
-	{ 1125, 1150, 1150, 1150, 1237, 1237, 1237, 1150, 1150 };
+/* speedo_id 0,    1,    2,    3,    4,    5,    6,    7,    8,   9,  10,  11 */
+	{ 1125, 1150, 1150, 1150, 1237, 1237, 1237, 1150, 1150, 912, 850, 850};
 
 int tegra_cpu_speedo_mv(void)
 {
@@ -367,6 +396,8 @@ int tegra_core_speedo_mv(void)
 		/* fall thru for T30L or T30SL */
 	case 2:
 		return 1300;
+	case 3:
+		return 1250;
 	default:
 		BUG();
 	}