arm: tegra: Restructure dam driver and add device for audio test manager

Added device for audio test manager, dam restructuring and added device ioctls
Added EXPORT_SYMBOL for functions used by audio test manager

Change-Id: I0bd73f0586132598f7161b18fcdd2cdfafc39677
Reviewed-on: http://git-master/r/48919
Tested-by: Rahul Mittal <rmittal@nvidia.com>
Reviewed-by: Vijay Mali <vmali@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>

6 files changed, 177 insertions, 94 deletions

diff --git a/arch/arm/mach-tegra/audio_switch.c b/arch/arm/mach-tegra/audio_switch.c
index e07b20ecbe5a..900d98e9b592 100644
--- a/arch/arm/mach-tegra/audio_switch.c
+++ b/arch/arm/mach-tegra/audio_switch.c
@@ -443,6 +443,7 @@ int audio_apbif_free_channel(int ifc, int fifo_mode)
 
 	return 0;
 }
+EXPORT_SYMBOL(audio_apbif_free_channel);
 
 /* FIXME : Stream with same index has to be taken care of
    need to figure out the stream->number is differential
@@ -511,6 +512,7 @@ void apbif_channel_enable(int ifc, int tx, int enable)
 	}
 	apbif_writel(ifc, val, APBIF_CHANNEL0_CTRL_0);
 }
+EXPORT_SYMBOL(apbif_channel_enable);
 
 /*
 *  apbif loopback mode
@@ -556,6 +558,7 @@ void apbif_set_pack_mode(int ifc, int tx, int pack_mode)
 
 	apbif_writel(ifc, val, APBIF_CHANNEL0_CTRL_0);
 }
+EXPORT_SYMBOL(apbif_set_pack_mode);
 
 /*
 *  Apbif set threshold
@@ -585,6 +588,7 @@ int apbif_fifo_set_attention_level(int ifc, int tx, unsigned level)
 	apbif_writel(ifc, val, APBIF_CHANNEL0_CTRL_0);
 	return 0;
 }
+EXPORT_SYMBOL(apbif_fifo_set_attention_level);
 
 void apbif_fifo_write(int ifc, int fifo_mode, u32 data)
 {
@@ -631,6 +635,7 @@ void apbif_soft_reset(int ifc, int fifo_mode, int enable)
 
 	apbif_writel(ifc, val, APBIF_CHANNEL0_CLEAR_0);
 }
+EXPORT_SYMBOL(apbif_soft_reset);
 
 /*
 * Apbif channel get fifo free count
@@ -683,11 +688,13 @@ phys_addr_t apbif_get_fifo_phy_base(int ifc, int tx)
 	return (ch->phy_base + ((tx == AUDIO_TX_MODE)?
 		APBIF_CHANNEL0_TXFIFO_0:APBIF_CHANNEL0_RXFIFO_0));
 }
+EXPORT_SYMBOL(apbif_get_fifo_phy_base);
 
 int apbif_get_channel(int regindex, int fifo_mode)
 {
 	return get_apbif_channel(regindex, fifo_mode);
 }
+EXPORT_SYMBOL(apbif_get_channel);
 
 void audio_switch_disable_clock(void)
 {
@@ -751,6 +758,7 @@ fail_audio_clock:
 	audio_switch_disable_clock();
 	return err;
 }
+EXPORT_SYMBOL(audio_switch_enable_clock);
 
 int audio_apbif_set_acif(int ifc, int fifo_mode, struct audio_cif *cifInfo)
 {
@@ -767,6 +775,7 @@ int audio_apbif_set_acif(int ifc, int fifo_mode, struct audio_cif *cifInfo)
 	}
 	return 0;
 }
+EXPORT_SYMBOL(audio_apbif_set_acif);
 
 int audio_switch_suspend(void)
 {
@@ -874,6 +883,7 @@ fail_audio_open:
 
 	return err;
 }
+EXPORT_SYMBOL(audio_switch_open);
 
 int audio_switch_close(void)
 {
@@ -897,3 +907,4 @@ int audio_switch_close(void)
 	dam_close();
 	return 0;
 }
+EXPORT_SYMBOL(audio_switch_close);
\ No newline at end of file
diff --git a/arch/arm/mach-tegra/dam.c b/arch/arm/mach-tegra/dam.c
index 0940fd117f7f..1edc25941a83 100644
--- a/arch/arm/mach-tegra/dam.c
+++ b/arch/arm/mach-tegra/dam.c
@@ -24,6 +24,7 @@
 #include <mach/iomap.h>
 #include <mach/audio.h>
 #include <mach/audio_switch.h>
+#include <mach/dam.h>
 
 #define NR_DAM_IFC	3
 
@@ -32,97 +33,6 @@
 	return __VA_ARGS__;						\
 }
 
-/* Offsets from TEGRA_DAM1_BASE, TEGRA_DAM2_BASE and TEGRA_DAM3_BASE */
-#define DAM_CTRL_0			0
-#define DAM_CLIP_0			4
-#define DAM_CLIP_THRESHOLD_0		8
-#define DAM_AUDIOCIF_OUT_CTRL_0		0x0C
-#define DAM_CH0_CTRL_0			0x10
-#define DAM_CH0_CONV_0			0x14
-#define DAM_AUDIOCIF_CH0_CTRL_0		0x1C
-#define DAM_CH1_CTRL_0			0x20
-#define DAM_CH1_CONV_0			0x24
-#define DAM_AUDIOCIF_CH1_CTRL_0		0x2C
-
-#define DAM_CTRL_REGINDEX 	(DAM_AUDIOCIF_CH1_CTRL_0 >> 2)
-#define DAM_CTRL_RSVD_6		6
-#define DAM_CTRL_RSVD_10	10
-
-#define DAM_NUM_INPUT_CHANNELS		2
-#define DAM_FS_8KHZ  			0
-#define DAM_FS_16KHZ 			1
-#define DAM_FS_44KHZ 			2
-#define DAM_FS_48KHZ 			3
-
-/* DAM_CTRL_0 */
-
-#define DAM_CTRL_0_SOFT_RESET_ENABLE	(1 << 31)
-
-#define DAM_CTRL_0_FSOUT_SHIFT	4
-#define DAM_CTRL_0_FSOUT_MASK	(0xf << DAM_CTRL_0_FSOUT_SHIFT)
-#define DAM_CTRL_0_FSOUT_FS8	(DAM_FS_8KHZ << DAM_CTRL_0_FSOUT_SHIFT)
-#define DAM_CTRL_0_FSOUT_FS16	(DAM_FS_16KHZ << DAM_CTRL_0_FSOUT_SHIFT)
-#define DAM_CTRL_0_FSOUT_FS44	(DAM_FS_44KHZ << DAM_CTRL_0_FSOUT_SHIFT)
-#define DAM_CTRL_0_FSOUT_FS48	(DAM_FS_48KHZ << DAM_CTRL_0_FSOUT_SHIFT)
-#define DAM_CTRL_0_CG_EN	(1 << 1)
-#define DAM_CTRL_0_DAM_EN	(1 << 0)
-
-/* DAM_CLIP_0 */
-
-#define DAM_CLIP_0_COUNTER_ENABLE	(1 << 31)
-#define DAM_CLIP_0_COUNT_MASK		0x7fffffff
-
-/* DAM_CLIP_THRESHOLD_0 */
-#define DAM_CLIP_THRESHOLD_0_VALUE_SHIFT	8
-#define DAM_CLIP_THRESHOLD_0_VALUE_MASK		\
-		(0x7fffff << DAM_CLIP_THRESHOLD_0_VALUE_SHIFT)
-#define DAM_CLIP_THRESHOLD_0_VALUE		(1 << 31)
-#define DAM_CLIP_THRESHOLD_0_COUNT_SHIFT	0
-
-
-#define STEP_RESET		1
-#define DAM_DATA_SYNC		1
-#define DAM_DATA_SYNC_SHIFT	4
-#define DAM_GAIN		1
-#define DAM_GAIN_SHIFT		0
-
-/* DAM_CH0_CTRL_0 */
-#define DAM_CH0_CTRL_0_FSIN_SHIFT	8
-#define DAM_CH0_CTRL_0_STEP_SHIFT	16
-#define DAM_CH0_CTRL_0_STEP_MASK	(0xffff << 16)
-#define DAM_CH0_CTRL_0_STEP_RESET	(STEP_RESET << 16)
-#define DAM_CH0_CTRL_0_FSIN_MASK	(0xf << 8)
-#define DAM_CH0_CTRL_0_FSIN_FS8		(DAM_FS_8KHZ << 8)
-#define DAM_CH0_CTRL_0_FSIN_FS16	(DAM_FS_16KHZ << 8)
-#define DAM_CH0_CTRL_0_FSIN_FS44	(DAM_FS_44KHZ << 8)
-#define DAM_CH0_CTRL_0_FSIN_FS48	(DAM_FS_48KHZ << 8)
-#define DAM_CH0_CTRL_0_DATA_SYNC_MASK	(0xf << DAM_DATA_SYNC_SHIFT)
-#define DAM_CH0_CTRL_0_DATA_SYNC	(DAM_DATA_SYNC << DAM_DATA_SYNC_SHIFT)
-#define DAM_CH0_CTRL_0_EN		(1 << 0)
-
-
-/* DAM_CH0_CONV_0 */
-#define DAM_CH0_CONV_0_GAIN		(DAM_GAIN << DAM_GAIN_SHIFT)
-
-/* DAM_CH1_CTRL_0 */
-#define DAM_CH1_CTRL_0_DATA_SYNC_MASK	(0xf << DAM_DATA_SYNC_SHIFT)
-#define DAM_CH1_CTRL_0_DATA_SYNC	(DAM_DATA_SYNC << DAM_DATA_SYNC_SHIFT)
-#define DAM_CH1_CTRL_0_EN		(1 << 0)
-
-/* DAM_CH1_CONV_0 */
-#define DAM_CH1_CONV_0_GAIN		(DAM_GAIN << DAM_GAIN_SHIFT)
-
-#define DAM_OUT_CHANNEL		0
-#define DAM_IN_CHANNEL_0	1
-#define DAM_IN_CHANNEL_1	2
-
-#define  ENABLE_DAM_DEBUG_PRINT	0
-
-#if ENABLE_DAM_DEBUG_PRINT
-#define DAM_DEBUG_PRINT(fmt, arg...) printk(fmt, ## arg)
-#else
-#define DAM_DEBUG_PRINT(fmt, arg...) do {} while (0)
-#endif
 
 /* FIXME: move this control to audio_manager later if needed */
 struct dam_context {
@@ -157,7 +67,7 @@ struct dam_src_step_table  step_table[] = {
 	{ 16000, 44100, 160 },
 	{ 16000, 48000, 1 },
 	{ 44100, 8000, 441 },
-	{ 48000, 8000, 6 },
+	{ 48000, 8000, 0 },
 	{ 44100, 16000, 441 },
 	{ 48000, 16000, 0 },
 };
@@ -239,7 +149,9 @@ void dam_enable(int ifc, int on, int chtype)
 		DAM_CTRL_0_DAM_EN : 0;
 
 	dam_writel(ifc, val, DAM_CTRL_0);
+
 }
+EXPORT_SYMBOL(dam_enable);
 
 void dam_enable_clip_counter(int ifc, int on)
 {
@@ -285,6 +197,7 @@ int dam_set_gain(int ifc, int chtype, int gain)
 	}
 	return 0;
 }
+EXPORT_SYMBOL(dam_set_gain);
 
 void dam_set_samplerate(int ifc, int chtype, int samplerate)
 {
@@ -307,6 +220,7 @@ void dam_set_samplerate(int ifc, int chtype, int samplerate)
 		break;
 	}
 }
+EXPORT_SYMBOL(dam_set_samplerate);
 
 void dam_set_output_samplerate(int ifc,int fsout)
 {
@@ -480,7 +394,6 @@ int dam_suspend(int ifc)
 	ch = &dam_cont_info[ifc];
 
 	dam_save_ctrl_registers(ifc);
-
 	dam_disable_clock(ifc);
 
 	return 0;
@@ -492,7 +405,6 @@ int dam_resume(int ifc)
 	ch = &dam_cont_info[ifc];
 
 	dam_enable_clock(ifc);
-
 	dam_restore_ctrl_registers(ifc);
 
 	return 0;
@@ -514,6 +426,7 @@ int dam_set_clock_parent(int ifc, int parent)
 	clk_set_parent(ch->dam_clk, mclk_source);
 	return 0;
 }
+EXPORT_SYMBOL(dam_set_clock_parent);
 
 void dam_disable_clock(int ifc)
 {
@@ -563,6 +476,7 @@ fail_dam_clock:
 	dam_disable_clock(ifc);
 	return err;
 }
+EXPORT_SYMBOL(dam_enable_clock);
 
 int dam_set_acif(int ifc, int chtype, struct audio_cif *cifInfo)
 {
@@ -591,6 +505,7 @@ int dam_set_acif(int ifc, int chtype, struct audio_cif *cifInfo)
 
 	return 0;
 }
+EXPORT_SYMBOL(dam_set_acif);
 
 int dam_get_controller(int chtype)
 {
@@ -610,6 +525,7 @@ int dam_get_controller(int chtype)
 				pr_err("unable to enable the dam channel\n");
 				return -ENOENT;
 			}
+
 			ch->in_use = true;
 			ch->ch_alloc[chtype] = true;
 			return i;
@@ -622,6 +538,7 @@ int dam_get_controller(int chtype)
 	}
 	return -ENOENT;
 }
+EXPORT_SYMBOL(dam_get_controller);
 
 int dam_free_controller(int ifc, int chtype)
 {
@@ -648,6 +565,7 @@ int dam_free_controller(int ifc, int chtype)
 
 	return 0;
 }
+EXPORT_SYMBOL(dam_free_controller);
 
 int dam_get_dma_requestor(int ifc, int chtype, int fifo_mode)
 {
@@ -700,6 +618,7 @@ int dam_open(void)
 		for (i = 0; i < NR_DAM_IFC; i++) {
 			ch = &dam_cont_info[i];
 			memset(ch, 0, sizeof(struct dam_context));
+
 			ch->dam_clk = tegra_get_clock_by_name(damclk_info[i]);
 			if (!ch->dam_clk) {
 				pr_err("unable to get dam%d clock\n", i);
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
index b982f91c371b..318eb41eaf49 100644
--- a/arch/arm/mach-tegra/devices.c
+++ b/arch/arm/mach-tegra/devices.c
@@ -714,6 +714,13 @@ struct platform_device tegra_spdif_device = {
 	.num_resources	= ARRAY_SIZE(spdif_resource),
 };
 
+#if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
+struct platform_device tegra_test_manager_device = {
+	.name		= "audio_test_manager",
+	.id		= 0,
+};
+#endif
+
 #if defined(CONFIG_SND_HDA_TEGRA)
 static u64 tegra_hda_dma_mask = DMA_BIT_MASK(32);
 
diff --git a/arch/arm/mach-tegra/devices.h b/arch/arm/mach-tegra/devices.h
index 7fc387ee6283..6b79dbd3b50b 100644
--- a/arch/arm/mach-tegra/devices.h
+++ b/arch/arm/mach-tegra/devices.h
@@ -88,6 +88,9 @@ extern struct platform_device tegra_uartc_device;
 extern struct platform_device tegra_uartd_device;
 extern struct platform_device tegra_uarte_device;
 extern struct platform_device tegra_spdif_device;
+#if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
+extern struct platform_device tegra_test_manager_device;
+#endif
 extern struct platform_device tegra_grhost_device;
 extern struct platform_device tegra_spdif_device;
 extern struct platform_device tegra_avp_device;
diff --git a/arch/arm/mach-tegra/dma.c b/arch/arm/mach-tegra/dma.c
index a46dd0b3001d..88d77b6eff59 100644
--- a/arch/arm/mach-tegra/dma.c
+++ b/arch/arm/mach-tegra/dma.c
@@ -196,6 +196,7 @@ int tegra_dma_cancel(struct tegra_dma_channel *ch)
 	spin_unlock_irqrestore(&ch->lock, irq_flags);
 	return 0;
 }
+EXPORT_SYMBOL(tegra_dma_cancel);
 
 static unsigned int get_channel_status(struct tegra_dma_channel *ch,
 			struct tegra_dma_req *req, bool is_stop_dma)
diff --git a/arch/arm/mach-tegra/include/mach/dam.h b/arch/arm/mach-tegra/include/mach/dam.h
new file mode 100644
index 000000000000..fc55851ab808
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/dam.h
@@ -0,0 +1,142 @@
+/*
+ * arch/arm/mach-tegra/include/mach/dam.h
+ *
+ * Copyright (c) 2011, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#ifndef __MACH_TEGRA_DAM_H
+#define __MACH_TEGRA_DAM_H
+
+/* Offsets from TEGRA_DAM1_BASE, TEGRA_DAM2_BASE and TEGRA_DAM3_BASE */
+#define DAM_CTRL_0			0
+#define DAM_CLIP_0			4
+#define DAM_CLIP_THRESHOLD_0		8
+#define DAM_AUDIOCIF_OUT_CTRL_0		0x0C
+#define DAM_CH0_CTRL_0			0x10
+#define DAM_CH0_CONV_0			0x14
+#define DAM_AUDIOCIF_CH0_CTRL_0		0x1C
+#define DAM_CH1_CTRL_0			0x20
+#define DAM_CH1_CONV_0			0x24
+#define DAM_AUDIOCIF_CH1_CTRL_0		0x2C
+
+#define DAM_CTRL_REGINDEX 	(DAM_AUDIOCIF_CH1_CTRL_0 >> 2)
+#define DAM_CTRL_RSVD_6		6
+#define DAM_CTRL_RSVD_10	10
+
+#define DAM_NUM_INPUT_CHANNELS		2
+#define DAM_FS_8KHZ  			0
+#define DAM_FS_16KHZ 			1
+#define DAM_FS_44KHZ 			2
+#define DAM_FS_48KHZ 			3
+
+/* DAM_CTRL_0 */
+
+#define DAM_CTRL_0_SOFT_RESET_ENABLE	(1 << 31)
+
+#define DAM_CTRL_0_FSOUT_SHIFT	4
+#define DAM_CTRL_0_FSOUT_MASK	(0xf << DAM_CTRL_0_FSOUT_SHIFT)
+#define DAM_CTRL_0_FSOUT_FS8	(DAM_FS_8KHZ << DAM_CTRL_0_FSOUT_SHIFT)
+#define DAM_CTRL_0_FSOUT_FS16	(DAM_FS_16KHZ << DAM_CTRL_0_FSOUT_SHIFT)
+#define DAM_CTRL_0_FSOUT_FS44	(DAM_FS_44KHZ << DAM_CTRL_0_FSOUT_SHIFT)
+#define DAM_CTRL_0_FSOUT_FS48	(DAM_FS_48KHZ << DAM_CTRL_0_FSOUT_SHIFT)
+#define DAM_CTRL_0_CG_EN	(1 << 1)
+#define DAM_CTRL_0_DAM_EN	(1 << 0)
+
+/* DAM_CLIP_0 */
+
+#define DAM_CLIP_0_COUNTER_ENABLE	(1 << 31)
+#define DAM_CLIP_0_COUNT_MASK		0x7fffffff
+
+/* DAM_CLIP_THRESHOLD_0 */
+#define DAM_CLIP_THRESHOLD_0_VALUE_SHIFT	8
+#define DAM_CLIP_THRESHOLD_0_VALUE_MASK		\
+		(0x7fffff << DAM_CLIP_THRESHOLD_0_VALUE_SHIFT)
+#define DAM_CLIP_THRESHOLD_0_VALUE		(1 << 31)
+#define DAM_CLIP_THRESHOLD_0_COUNT_SHIFT	0
+
+
+#define STEP_RESET		1
+#define DAM_DATA_SYNC		1
+#define DAM_DATA_SYNC_SHIFT	4
+#define DAM_GAIN		1
+#define DAM_GAIN_SHIFT		0
+
+/* DAM_CH0_CTRL_0 */
+#define DAM_CH0_CTRL_0_FSIN_SHIFT	8
+#define DAM_CH0_CTRL_0_STEP_SHIFT	16
+#define DAM_CH0_CTRL_0_STEP_MASK	(0xffff << 16)
+#define DAM_CH0_CTRL_0_STEP_RESET	(STEP_RESET << 16)
+#define DAM_CH0_CTRL_0_FSIN_MASK	(0xf << 8)
+#define DAM_CH0_CTRL_0_FSIN_FS8		(DAM_FS_8KHZ << 8)
+#define DAM_CH0_CTRL_0_FSIN_FS16	(DAM_FS_16KHZ << 8)
+#define DAM_CH0_CTRL_0_FSIN_FS44	(DAM_FS_44KHZ << 8)
+#define DAM_CH0_CTRL_0_FSIN_FS48	(DAM_FS_48KHZ << 8)
+#define DAM_CH0_CTRL_0_DATA_SYNC_MASK	(0xf << DAM_DATA_SYNC_SHIFT)
+#define DAM_CH0_CTRL_0_DATA_SYNC	(DAM_DATA_SYNC << DAM_DATA_SYNC_SHIFT)
+#define DAM_CH0_CTRL_0_EN		(1 << 0)
+
+
+/* DAM_CH0_CONV_0 */
+#define DAM_CH0_CONV_0_GAIN		(DAM_GAIN << DAM_GAIN_SHIFT)
+
+/* DAM_CH1_CTRL_0 */
+#define DAM_CH1_CTRL_0_DATA_SYNC_MASK	(0xf << DAM_DATA_SYNC_SHIFT)
+#define DAM_CH1_CTRL_0_DATA_SYNC	(DAM_DATA_SYNC << DAM_DATA_SYNC_SHIFT)
+#define DAM_CH1_CTRL_0_EN		(1 << 0)
+
+/* DAM_CH1_CONV_0 */
+#define DAM_CH1_CONV_0_GAIN		(DAM_GAIN << DAM_GAIN_SHIFT)
+
+#define DAM_OUT_CHANNEL		0
+#define DAM_IN_CHANNEL_0	1
+#define DAM_IN_CHANNEL_1	2
+
+#define  ENABLE_DAM_DEBUG_PRINT	0
+
+#if ENABLE_DAM_DEBUG_PRINT
+#define DAM_DEBUG_PRINT(fmt, arg...) printk(fmt, ## arg)
+#else
+#define DAM_DEBUG_PRINT(fmt, arg...) do {} while (0)
+#endif
+
+/* dam apis */
+
+void dam_enable(int ifc, int on, int chtype);
+void dam_enable_clip_counter(int ifc, int on);
+void dam_set_samplerate(int ifc, int chtype, int samplerate);
+
+void dam_save_ctrl_registers(int ifc);
+void dam_restore_ctrl_registers(int ifc);
+int dam_suspend(int ifc);
+int dam_resume(int ifc);
+
+int dam_set_clock_rate(int rate);
+int dam_set_clock_parent(int ifc, int parent);
+void dam_disable_clock(int ifc);
+int dam_enable_clock(int ifc);
+int dam_set_acif(int ifc, int chtype, struct audio_cif *cifInfo);
+int dam_get_controller(int chtype);
+int dam_free_controller(int ifc, int chtype);
+int dam_set_gain(int ifc, int chtype, int gain);
+int dam_get_dma_requestor(int ifc, int chtype, int fifo_mode);
+int dam_free_dma_requestor(int ifc, int chtype, int fifo_mode);
+
+int dam_open(void);
+int dam_close(void);
+
+#endif
\ No newline at end of file