diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2016-01-09 00:20:25 +0800 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@nxp.com> | 2016-01-14 11:03:07 -0600 |
| commit | f777f7294af3ab1c4dd32946f51f6b65bf8a57b1 (patch) | |
| tree | 984cb0cc6a220c438dea38f779cdc907974032fc /arch/arm | |
| parent | 54d51990caf157e9e03bd0c56b551cad1cceb314 (diff) | |
MLK-12162 ARM: imx: correct SCU PGC setting on i.MX7D
SCU PGC register is different from others, it contains
other timing settings, so we can NOT just program 0/1
to disable/enable SCU power gating, but need to only
program bit 0, correct it for all modules' PGC settings.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-imx/gpcv2.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/gpcv2.c b/arch/arm/mach-imx/gpcv2.c index 34070cbc9386..1efecde4ec41 100644 --- a/arch/arm/mach-imx/gpcv2.c +++ b/arch/arm/mach-imx/gpcv2.c @@ -78,6 +78,7 @@ #define BM_LPCR_A7_AD_EN_C0_WFI_PDN 0x1 #define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 0x2 +#define BM_GPC_PGC_PCG 0x1 #define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK 0x80000000 #define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK 0x8000 @@ -280,7 +281,12 @@ void imx_gpcv2_set_plat_power_gate_by_lpm(bool pdn) void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset) { - writel_relaxed(enable, gpc_base + offset); + u32 val = readl_relaxed(gpc_base + offset) & (~BM_GPC_PGC_PCG); + + if (enable) + val |= BM_GPC_PGC_PCG; + + writel_relaxed(val, gpc_base + offset); } void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn) |