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authorSrinivas Kandagatla <srinivas.kandagatla@linaro.org>2016-02-23 14:14:33 +0000
committerAndy Gross <andy.gross@linaro.org>2016-02-26 13:15:48 -0600
commitb2dc04c5b0fcba2627175f543faff5869f32fd6f (patch)
tree38d950e010bf875a8b4528f761f4226ffbd4537f /arch/arm
parent64b22b2594b1832ad21fce4969818e774d329551 (diff)
ARM: dts: apq8064: add spi5 device node.
This patch adds spi5 device node, spi5 is used on ifc6410 on the expansion connector. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/qcom-apq8064-pins.dtsi38
-rw-r--r--arch/arm/boot/dts/qcom-apq8064.dtsi14
2 files changed, 52 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
index ce15c674690f..0b7b10e8ba5c 100644
--- a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
@@ -64,6 +64,44 @@
};
};
+ spi5_default: spi5_default {
+ pinmux {
+ pins = "gpio51", "gpio52", "gpio54";
+ function = "gsbi5";
+ };
+
+ pinmux_cs {
+ function = "gpio";
+ pins = "gpio53";
+ };
+
+ pinconf {
+ pins = "gpio51", "gpio52", "gpio54";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ pinconf_cs {
+ pins = "gpio53";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ spi5_sleep: spi5_sleep {
+ pinmux {
+ function = "gpio";
+ pins = "gpio51", "gpio52", "gpio53", "gpio54";
+ };
+
+ pinconf {
+ pins = "gpio51", "gpio52", "gpio53", "gpio54";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
gsbi6_uart_2pins: gsbi6_uart_2pins {
mux {
pins = "gpio14", "gpio15";
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 7ed7999f4cb1..d46d460d621e 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -236,6 +236,7 @@
#address-cells = <1>;
#size-cells = <0>;
};
+
};
gsbi2: gsbi@12480000 {
@@ -306,6 +307,19 @@
clock-names = "core", "iface";
status = "disabled";
};
+
+ gsbi5_spi: spi@1a280000 {
+ compatible = "qcom,spi-qup-v1.1.1";
+ reg = <0x1a280000 0x1000>;
+ interrupts = <0 155 0>;
+ pinctrl-0 = <&spi5_default &spi5_sleep>;
+ pinctrl-names = "default", "sleep";
+ clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
gsbi6: gsbi@16500000 {