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authorPhilippe Schenker <philippe.schenker@toradex.com>2019-07-04 16:07:09 +0200
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2020-02-12 11:05:58 +0100
commiteeb27130f183ff61d75f24025107f6991ff55b17 (patch)
tree4138f3a3d23195b0b8e0ab05e5bdb7bee2156862 /arch/arm
parent4bfb19388251ba644a8c831a65c63d7e7b75b7d6 (diff)
ARM: dts (ds): sort iomuxc entries as downstream linux expects
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts24
-rw-r--r--arch/arm/boot/dts/imx6qdl-colibri.dtsi80
2 files changed, 51 insertions, 53 deletions
diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
index 135f234c2f85..8277c76130df 100644
--- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
@@ -241,18 +241,20 @@
&pinctrl_usbh_oc_1 &pinctrl_usbc_id_1
>;
- pinctrl_pcap_1: pcap-1 {
- fsl,pins = <
- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* SODIMM 28 */
- MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* SODIMM 30 */
- >;
- };
+ gpio {
+ pinctrl_pcap_1: pcap-1 {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* SODIMM 28 */
+ MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* SODIMM 30 */
+ >;
+ };
- pinctrl_mxt_ts: mxt-ts {
- fsl,pins = <
- MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x130b0 /* SODIMM 107 */
- MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x130b0 /* SODIMM 106 */
- >;
+ pinctrl_mxt_ts: mxt-ts {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x130b0 /* SODIMM 107 */
+ MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x130b0 /* SODIMM 106 */
+ >;
+ };
};
};
diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
index 51a51429d07e..81bd30f10f16 100644
--- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
@@ -559,50 +559,46 @@
imx6qdl-colibri {
- csi {
- /* CSI pins used as GPIO */
- pinctrl_csi_gpio_1: csi_gpio-1 {
- fsl,pins = <
- MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0
- MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0
- MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0
- MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0
- MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0
- MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0
- MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0
- MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0
- MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0
- MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0
- MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x1b0b0
- MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
- >;
- };
- pinctrl_csi_gpio_2: csi_gpio-2 {
- fsl,pins = <
- MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0
- >;
- };
+ /* CSI pins used as GPIO */
+ pinctrl_csi_gpio_1: csi_gpio-1 {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0
+ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0
+ MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0
+ MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0
+ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0
+ MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0
+ MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0
+ MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0
+ MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0
+ MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0
+ MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x1b0b0
+ MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
+ >;
+ };
+ pinctrl_csi_gpio_2: csi_gpio-2 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0
+ >;
};
- gpio {
- pinctrl_gpio_1: gpio-1 {
- fsl,pins = <
- MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b0
- MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0
- MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
- MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0
- MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0
- MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0
- MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
- MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0
- >;
- };
- pinctrl_gpio_2: gpio-2 {
- fsl,pins = <
- MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
- >;
- };
+ pinctrl_gpio_1: gpio-1 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b0
+ MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0
+ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0
+ MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0
+ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0
+ MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
+ MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0
+ >;
+ };
+ pinctrl_gpio_2: gpio-2 {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
+ MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
+ >;
};
pinctrl_audmux: audmuxgrp {