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authorBibek Basu <bbasu@nvidia.com>2015-03-26 13:13:41 +0530
committerMatthew Pedro <mapedro@nvidia.com>2015-04-07 22:39:20 -0700
commit62ac79266ebff845d01cf3296e54c64b49119129 (patch)
treef536a3ab8a4f24113a8f0df5f8e1bc01ffe41bf2 /arch/arm
parent8b6e79f59a45c2e66975b0c27ef9d855d15208ca (diff)
pinctrl: tegra: Add MIPI pad control
This patch adds MIPI CSI/DSIB pad control mux register from the APB misc block to tegra pinctrl. Without writing to this register, the dsib pads are muxed as csi, and cannot be used. The register is not yet documented in the TRM, here is the description: 70000820: APB_MISC_GP_MIPI_PAD_CTRL_0 [31:02] RESERVED [01:01] DSIB_MODE [CSI=0,DSIB=1] [00:00] RESERVED Signed-off-by: Sean Paul <seanpaul@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> BUG=chrome-os-partner:30799 TEST=Tested on ryu (cherry picked from commit 489c8251776de8838547207acce199f50846ded1) Change-Id: I424f488131e51ac793814d98d018162f0644509e Reviewed-on: https://chromium-review.googlesource.com/219832 Reviewed-on: http://git-master/r/668725 Signed-off-by: Bibek Basu <bbasu@nvidia.com> Reviewed-on: http://git-master/r/723409 Reviewed-by: Matthew Pedro <mapedro@nvidia.com> Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/tegra124-soc.dtsi3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/tegra124-soc.dtsi b/arch/arm/boot/dts/tegra124-soc.dtsi
index 080f88bf9e67..5c8402329aec 100644
--- a/arch/arm/boot/dts/tegra124-soc.dtsi
+++ b/arch/arm/boot/dts/tegra124-soc.dtsi
@@ -21,7 +21,8 @@
pinmux: pinmux {
compatible = "nvidia,tegra124-pinmux";
reg = <0x0 0x70000868 0x0 0x164 /* Pad control registers */
- 0x0 0x70003000 0x0 0x434>; /* Mux registers */
+ 0x0 0x70003000 0x0 0x434 /* Mux registers */
+ 0x0 0x70000820 0x0 0x8>; /* MIPI pad control */
};
gpio: gpio@6000d000 {