diff options
author | Alex Frid <afrid@nvidia.com> | 2011-05-07 23:04:53 -0700 |
---|---|---|
committer | Varun Colbert <vcolbert@nvidia.com> | 2011-05-13 18:41:46 -0700 |
commit | fca04a452d60ec215937c461d4af6247760e7e8e (patch) | |
tree | ed70403ee310797bfff374545a5bc55d2a1e438d /arch/arm | |
parent | 2f3531d505a6b8b74d51583abeb874bcf4c86e65 (diff) |
ARM: tegra: power: Add out-of-range CPU dvfs entry
Change-Id: Ic50e6261e34caa3851ef68a6e2a6cbbd600a13d6
Reviewed-on: http://git-master/r/30929
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-tegra/tegra3_clocks.c | 22 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra3_dvfs.c | 23 |
2 files changed, 31 insertions, 14 deletions
diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index db3a81016544..6731493cb487 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -3619,6 +3619,12 @@ void __init tegra_soc_init_clocks(void) * must be ascending. */ +static struct cpufreq_frequency_table freq_table_300MHz[] = { + { 0, 216000 }, + { 1, 300000 }, + { 2, CPUFREQ_TABLE_END }, +}; + static struct cpufreq_frequency_table freq_table_1p0GHz[] = { { 0, 216000 }, { 1, 312000 }, @@ -3632,16 +3638,17 @@ static struct cpufreq_frequency_table freq_table_1p0GHz[] = { }; static struct tegra_cpufreq_table_data cpufreq_tables[] = { + { freq_table_300MHz, 0, 1 }, { freq_table_1p0GHz, 2, 6 }, }; static void clip_cpu_rate_limits( struct cpufreq_frequency_table *freq_table, - struct cpufreq_policy *policy) + struct cpufreq_policy *policy, + struct clk *cpu_clk_g, + struct clk *cpu_clk_lp) { int idx, ret; - struct clk *cpu_clk_g = tegra_get_clock_by_name("cpu_g"); - struct clk *cpu_clk_lp = tegra_get_clock_by_name("cpu_lp"); /* clip CPU LP mode maximum frequency to table entry, and set CPU G mode minimum frequency one table step below */ @@ -3659,7 +3666,8 @@ static void clip_cpu_rate_limits( struct tegra_cpufreq_table_data *tegra_cpufreq_table_get(void) { int i, ret; - struct clk *cpu_clk = tegra_get_clock_by_name("cpu"); + struct clk *cpu_clk_g = tegra_get_clock_by_name("cpu_g"); + struct clk *cpu_clk_lp = tegra_get_clock_by_name("cpu_lp"); for (i = 0; i < ARRAY_SIZE(cpufreq_tables); i++) { struct cpufreq_policy policy; @@ -3667,9 +3675,9 @@ struct tegra_cpufreq_table_data *tegra_cpufreq_table_get(void) ret = cpufreq_frequency_table_cpuinfo( &policy, cpufreq_tables[i].freq_table); BUG_ON(ret); - if ((policy.max * 1000) == cpu_clk->max_rate) { - clip_cpu_rate_limits( - cpufreq_tables[i].freq_table, &policy); + if ((policy.max * 1000) == cpu_clk_g->max_rate) { + clip_cpu_rate_limits(cpufreq_tables[i].freq_table, + &policy, cpu_clk_g, cpu_clk_lp); return &cpufreq_tables[i]; } } diff --git a/arch/arm/mach-tegra/tegra3_dvfs.c b/arch/arm/mach-tegra/tegra3_dvfs.c index 572cc0064ee3..4423e4a0f2ea 100644 --- a/arch/arm/mach-tegra/tegra3_dvfs.c +++ b/arch/arm/mach-tegra/tegra3_dvfs.c @@ -33,11 +33,11 @@ static const int core_millivolts[MAX_DVFS_FREQS] = {1000, 1050, 1100, 1150, 1200, 1250, 1300}; static const int core_speedo_nominal_millivolts[] = -/* spedo_id 0, 1, 2 */ +/* speedo_id 0, 1, 2 */ { 1200, 1200, 1300 }; static const int cpu_speedo_nominal_millivolts[] = -/* spedo_id 0, 1, 2 */ +/* speedo_id 0, 1, 2 */ { 1125, 1125, 1125 }; /* FIXME: EDP limit API */ @@ -115,6 +115,12 @@ static struct dvfs_relationship tegra3_dvfs_relationships[] = { static struct dvfs cpu_dvfs_table[] = { /* Cpu voltages (mV): 750, 775, 800, 825, 850, 875, 900, 925, 950, 975, 1000, 1025, 1050, 1075, 1100, 1125 */ CPU_DVFS("cpu_g", 0, 0, MHZ, 1, 1, 614, 614, 714, 714, 815, 815, 915, 915, 1000), + + /* + * "Safe entry" to be used when no match for chip speedo, process + * corner is found (just to boot at low rate); must be the last one + */ + CPU_DVFS("cpu_g",-1,-1, MHZ, 1, 1, 216, 216, 300), }; #define CORE_DVFS(_clk_name, _speedo_id, _auto, _mult, _freqs...) \ @@ -298,11 +304,14 @@ static int __init get_cpu_nominal_mv_index( } } - if (i == 0) { - pr_err("tegra3_dvfs: unable to adjust cpu dvfs table to" - " nominal voltage %d\n", mv); - return -ENOSYS; - } + BUG_ON(i == 0); + if (j == (ARRAY_SIZE(cpu_dvfs_table) - 1)) + pr_err("tegra3_dvfs: WARNING!!!\n" + "tegra3_dvfs: no cpu dvfs table found for chip speedo_id" + " %d and process_id %d: set CPU rate limit at %lu\n" + "tegra3_dvfs: WARNING!!!\n", + speedo_id, process_id, d->freqs[i-1] * d->freqs_mult); + *cpu_dvfs = d; return (i - 1); } |