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authorShawn Guo <shawn.guo@freescale.com>2014-07-26 10:33:03 +0800
committerShawn Guo <shawn.guo@freescale.com>2014-08-18 11:38:33 +0800
commit59d05b518321618177b898a6801503e31b15b25b (patch)
treedb4c2111589a7acfdb9961685bf808096758007b /arch/arm
parent060d517de88867b06225119beeba3a0472cc6bc5 (diff)
ARM: imx: fix TLB missing of IOMUXC base address during suspend
After the suspend routine running in OCRAM puts DDR into self-refresh, it will access IOMUXC block to float DDR IO for power saving. A TLB missing of IOMUXC base address may happen in this case, and triggers an access to DDR, and thus hangs the system. The failure is discovered by running suspend/resume on a Cubox-i board. Though the issue is not Cubox-i specific, it can be hit the on the board quite easily with the 3.15 or 3.16 kernel. Fix the issue with a dummy access to IOMUXC block at the beginning of suspend routine, so that the address translation can be filled into TLB before DDR is put into self-refresh. Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Cc: <stable@vger.kernel.org> Acked-by: Anson Huang <Anson.Huang@freescale.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-imx/suspend-imx6.S2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S
index 74b50f1982db..ca4ea2daf25b 100644
--- a/arch/arm/mach-imx/suspend-imx6.S
+++ b/arch/arm/mach-imx/suspend-imx6.S
@@ -173,6 +173,8 @@ ENTRY(imx6_suspend)
ldr r6, [r11, #0x0]
ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
ldr r6, [r11, #0x0]
+ ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
+ ldr r6, [r11, #0x0]
/* use r11 to store the IO address */
ldr r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET]