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authorKrishna Reddy <vdumpa@nvidia.com>2011-12-01 15:32:36 -0800
committerVarun Wadekar <vwadekar@nvidia.com>2011-12-08 17:54:34 +0530
commit1212eb85a3328ab9b702ffc77b5704634587ab6c (patch)
tree9c4c1b9455b1b090010446fa44e405f65b5aace1 /arch/arm
parenta313eda68445caa15533156a83a35d7999cc9801 (diff)
arm: tegra: Set G-CPU L2 cache latency to 0x442/552.
also restore the L2 cache latency values after exit from LP2. Bug 909628 Change-Id: Ia113d3511255f77ba5f5bfbfafebe43ba247818f Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/67767 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-tegra/board.h2
-rw-r--r--arch/arm/mach-tegra/common.c19
-rw-r--r--arch/arm/mach-tegra/pm.c3
3 files changed, 14 insertions, 10 deletions
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index 15471101b6c8..11c10f38b0b1 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -43,7 +43,7 @@ void __init tegra_init_clock(void);
void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
unsigned long fb2_size);
int __init tegra_pcie_init(bool init_port0, bool init_port1);
-void tegra_init_cache(void);
+void tegra_init_cache(bool init);
void __init tegra_release_bootloader_fb(void);
void __init tegra_protected_aperture_init(unsigned long aperture);
void tegra_move_framebuffer(unsigned long to, unsigned long from,
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 2a7813755724..7fcf13117204 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -185,7 +185,7 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
{ NULL, NULL, 0, 0},
};
-void tegra_init_cache(void)
+void tegra_init_cache(bool init)
{
#ifdef CONFIG_CACHE_L2X0
void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
@@ -204,18 +204,21 @@ void tegra_init_cache(void)
writel(0x221, p + L2X0_TAG_LATENCY_CTRL);
writel(0x221, p + L2X0_DATA_LATENCY_CTRL);
} else {
- writel(0x441, p + L2X0_TAG_LATENCY_CTRL);
- writel(0x551, p + L2X0_DATA_LATENCY_CTRL);
+ /* FIXME: This should be based on speedo id. */
+ writel(0x442, p + L2X0_TAG_LATENCY_CTRL);
+ writel(0x552, p + L2X0_DATA_LATENCY_CTRL);
}
#else
writel(0x770, p + L2X0_TAG_LATENCY_CTRL);
writel(0x770, p + L2X0_DATA_LATENCY_CTRL);
#endif
#endif
- aux_ctrl = readl(p + L2X0_CACHE_TYPE);
- aux_ctrl = (aux_ctrl & 0x700) << (17-8);
- aux_ctrl |= 0x7C000001;
- l2x0_init(p, aux_ctrl, 0x8200c3fe);
+ if (init) {
+ aux_ctrl = readl(p + L2X0_CACHE_TYPE);
+ aux_ctrl = (aux_ctrl & 0x700) << (17-8);
+ aux_ctrl |= 0x7C000001;
+ l2x0_init(p, aux_ctrl, 0x8200c3fe);
+ }
#endif
}
@@ -330,7 +333,7 @@ void __init tegra_init_early(void)
tegra_init_pinmux();
tegra_clk_init_from_table(common_clk_init_table);
tegra_init_power();
- tegra_init_cache();
+ tegra_init_cache(true);
tegra_init_ahb_gizmo_settings();
}
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 82a7148cb7fd..8028c7814ddc 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -568,6 +568,7 @@ unsigned int tegra_idle_lp2_last(unsigned int sleep_time, unsigned int flags)
tegra_sleep_cpu(PLAT_PHYS_OFFSET - PAGE_OFFSET);
#ifdef CONFIG_CACHE_L2X0
+ tegra_init_cache(false);
l2x0_enable();
#endif
tegra_cluster_switch_time(flags, tegra_cluster_switch_time_id_switch);
@@ -811,7 +812,7 @@ int tegra_suspend_dram(enum tegra_suspend_mode mode, unsigned int flags)
else
tegra_sleep_core(PLAT_PHYS_OFFSET - PAGE_OFFSET);
- tegra_init_cache();
+ tegra_init_cache(true);
if (mode == TEGRA_SUSPEND_LP0) {
tegra_cpu_reset_handler_restore();