diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-03-06 17:40:43 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-03-22 09:17:37 +0100 |
| commit | b54a9bb7efdf146aa8a643f3ac40784394198333 (patch) | |
| tree | 332aef34abd6717f20148c3c8f1ddc79954726e6 /arch/arm | |
| parent | c62dc6051d854d99202d2fdced543e8706a6c219 (diff) | |
ARM: dts: r8a7794: Remove unit-address and reg from integrated cache
[ Upstream commit 65d0b7ed40f8a3a41a0ac5ed5ca4d1874c6aaf2d ]
The Cortex-A7 cache controller is an integrated controller, and thus the
device node representing it should not have a unit-addresses or reg
property.
Fixes: 34ea4b4a827b4ee7 ("ARM: dts: r8a7794: Fix W=1 dtc warnings")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/r8a7794.dtsi | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 7e860d3737ff..6c0150dcf146 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -56,9 +56,8 @@ next-level-cache = <&L2_CA7>; }; - L2_CA7: cache-controller@0 { + L2_CA7: cache-controller-0 { compatible = "cache"; - reg = <0>; power-domains = <&sysc R8A7794_PD_CA7_SCU>; cache-unified; cache-level = <2>; |