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authorLiu Jiang <jiang.liu@huawei.com>2012-03-13 22:07:09 +0800
committerTony Luck <tony.luck@intel.com>2012-03-14 13:35:47 -0700
commit0577bb661ee0ce4303c21353ac326f23efbc209c (patch)
treeba28b26c6a4e254e303b7f8af0de9b827e6d6250 /arch/ia64
parent15839b4774c618117122074c630a49983f515318 (diff)
[IA64] Fix ISA IRQ trigger model and polarity setting
When handling Interrupt Source Override in MADT table, the default ISA IRQ trigger model and polarity should be edge-rising. Current IA64 implmentation doesn't follow the specification and set default ISA IRQ trigger model as level-low. With that wrong configuration and when system runs out of interrupt vectors, it will cause vector sharing among edge triggered ISA IRQ and level triggered PCI IRQ, then interrupt storm. So change the code to follow the specification. Signed-off-by: Liu Jiang <jiang.liu@huawei.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch/ia64')
-rw-r--r--arch/ia64/kernel/acpi.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/ia64/kernel/acpi.c b/arch/ia64/kernel/acpi.c
index 5207035dc061..2d801bfe16ac 100644
--- a/arch/ia64/kernel/acpi.c
+++ b/arch/ia64/kernel/acpi.c
@@ -349,11 +349,11 @@ acpi_parse_int_src_ovr(struct acpi_subtable_header * header,
iosapic_override_isa_irq(p->source_irq, p->global_irq,
((p->inti_flags & ACPI_MADT_POLARITY_MASK) ==
- ACPI_MADT_POLARITY_ACTIVE_HIGH) ?
- IOSAPIC_POL_HIGH : IOSAPIC_POL_LOW,
+ ACPI_MADT_POLARITY_ACTIVE_LOW) ?
+ IOSAPIC_POL_LOW : IOSAPIC_POL_HIGH,
((p->inti_flags & ACPI_MADT_TRIGGER_MASK) ==
- ACPI_MADT_TRIGGER_EDGE) ?
- IOSAPIC_EDGE : IOSAPIC_LEVEL);
+ ACPI_MADT_TRIGGER_LEVEL) ?
+ IOSAPIC_LEVEL : IOSAPIC_EDGE);
return 0;
}