diff options
| author | Justin Waters <justin.waters@timesys.com> | 2008-02-26 13:07:02 -0500 |
|---|---|---|
| committer | Justin Waters <justin.waters@timesys.com> | 2008-02-26 13:07:02 -0500 |
| commit | b80a32b9cc634adfa8eaef33ec981e7febf2ade2 (patch) | |
| tree | f256bce13ba11f514a388160df84e1410bedbe2b /arch/mips/au1000/common/time.c | |
| parent | 594133ef22fae0d737bd1b57352cf3f48a192c63 (diff) | |
Update the i.MX31 Kernel to 2.6.232.6.23-mx31ads-2008022618072.6.23-mx31-200802261807
This is the result of a brute-force attempt to update the kernel to 2.6.23.
Now that we have a git tree, our effort will be a little nicer in the future.
Signed-off-by: Justin Waters <justin.waters@timesys.com>
Diffstat (limited to 'arch/mips/au1000/common/time.c')
| -rw-r--r-- | arch/mips/au1000/common/time.c | 29 |
1 files changed, 0 insertions, 29 deletions
diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c index fa1c62f05515..8fc29982d700 100644 --- a/arch/mips/au1000/common/time.c +++ b/arch/mips/au1000/common/time.c @@ -203,11 +203,7 @@ wakeup_counter0_set(int ticks) /* I haven't found anyone that doesn't use a 12 MHz source clock, * but just in case..... */ -#ifdef CONFIG_AU1000_SRC_CLK -#define AU1000_SRC_CLK CONFIG_AU1000_SRC_CLK -#else #define AU1000_SRC_CLK 12000000 -#endif /* * We read the real processor speed from the PLL. This is important @@ -247,33 +243,8 @@ unsigned long cal_r4koff(void) au_writel (0, SYS_TOYWRITE); while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); -#if defined(CONFIG_AU1000_USE32K) - { - unsigned long start, end, count; - - start = au_readl(SYS_RTCREAD); - start += 2; - /* wait for the beginning of a new tick - */ - while (au_readl(SYS_RTCREAD) < start); - - /* Start r4k counter. - */ - write_c0_count(0); - - /* Wait 0.5 seconds. - */ - end = start + (32768 / trim_divide)/2; - - while (end > au_readl(SYS_RTCREAD)); - - count = read_c0_count(); - cpu_speed = count * 2; - } -#else cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK; -#endif } else { /* The 32KHz oscillator isn't running, so assume there |