diff options
| author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-04-18 19:49:42 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-04-18 19:49:42 -0700 |
| commit | 038e5e2bf2819058fb1b4b52b583bef9ad063356 (patch) | |
| tree | 3a152b455f845a25d0958af5b461b034c2d565fa /arch/mips/cobalt/irq.c | |
| parent | 5c723d26fa223bdb17b9230c77e4e1156884475a (diff) | |
| parent | d34cb28a3718a7055ed14e2ec058fe3e4574af63 (diff) | |
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (47 commits)
[MAINTAINERS] The ham radio code now has website at http://www.linux-ax25.org.
[MIPS] Use __ffs() instead of ffs() for waybit calculation.
[MIPS] Fix Makefile bugs for MIPS32/MIPS64 R1 and R2.
[MIPS] Handle IDE PIO cache aliases on SMP.
[MIPS] Make mips_srs_init static.
[MIPS] MIPS boards: Set HZ to 100.
[MIPS] kgdb: Let gcc compute the array size itself.
[MIPS] FPU affinity for MT ASE.
[MIPS] MT: Improved multithreading support.
[MIPS] kpsd and other AP/SP improvements.
[MIPS] R2: Instruction hazard barrier.
[MIPS] Fix genrtc compilation.
[MIPS] R2: Implement shadow register allocation without spinlock.
[MIPS] Fix VR41xx build errors.
[MIPS] Fix tx49_blast_icache32_page_indexed.
[MIPS] Enable SCHED_NO_NO_OMIT_FRAME_POINTER for MIPS.
[MIPS] Use "R" constraint for cache_op.
[MIPS] Rewrite all the assembler interrupt handlers to C.
[MIPS] Fix the crime against humanity that mipsIRQ.S is.
[MIPS] Fixup damage done by 22a9835c350782a5c3257343713932af3ac92ee0.
...
Diffstat (limited to 'arch/mips/cobalt/irq.c')
| -rw-r--r-- | arch/mips/cobalt/irq.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/arch/mips/cobalt/irq.c b/arch/mips/cobalt/irq.c index f9a108820d6e..0b75f4fb7195 100644 --- a/arch/mips/cobalt/irq.c +++ b/arch/mips/cobalt/irq.c @@ -20,8 +20,6 @@ #include <asm/mach-cobalt/cobalt.h> -extern void cobalt_handle_int(void); - /* * We have two types of interrupts that we handle, ones that come in through * the CPU interrupt lines, and ones that come in on the via chip. The CPU @@ -79,7 +77,7 @@ static inline void via_pic_irq(struct pt_regs *regs) do_IRQ(irq, regs); } -asmlinkage void cobalt_irq(struct pt_regs *regs) +asmlinkage void plat_irq_dispatch(struct pt_regs *regs) { unsigned pending; @@ -122,8 +120,6 @@ void __init arch_init_irq(void) */ GALILEO_OUTL(0, GT_INTRMASK_OFS); - set_except_vector(0, cobalt_handle_int); - init_i8259_irqs(); /* 0 ... 15 */ mips_cpu_irq_init(COBALT_CPU_IRQ); /* 16 ... 23 */ |