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authorKevin D. Kissell <kevink@mips.com>2007-07-12 16:21:08 +0100
committerRalf Baechle <ralf@linux-mips.org>2007-07-12 17:41:17 +0100
commit0db34215c7e0ef618e7b29fbf271194ca5434f8e (patch)
tree261d8cd77fad2d661157ee5e5bde8e3fdc8c96b9 /arch/mips/kernel/genex.S
parentbd0765098bf22eb8b1319f649a4c3301b40ec04c (diff)
[MIPS] SMTC: Interrupt mask backstop hack
To support multiple TC microthreads acting as "CPUs" within a VPE, VPE-wide interrupt mask bits must be specially manipulated during interrupt handling. To support legacy drivers and interrupt controller management code, SMTC has a "backstop" to track and if necessary restore the interrupt mask. This has some performance impact on interrupt service overhead. Disable it only if you know what you are doing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/genex.S')
-rw-r--r--arch/mips/kernel/genex.S2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index 297bd56c2347..c0f19d638b98 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -243,9 +243,11 @@ NESTED(except_vec_vi_handler, 0, sp)
*/
mfc0 t1, CP0_STATUS
and t0, a0, t1
+#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
mfc0 t2, CP0_TCCONTEXT
or t0, t0, t2
mtc0 t0, CP0_TCCONTEXT
+#endif /* CONFIG_MIPS_MT_SMTC_IM_BACKSTOP */
xor t1, t1, t0
mtc0 t1, CP0_STATUS
_ehb