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authorLinus Torvalds <torvalds@g5.osdl.org>2006-04-18 19:49:42 -0700
committerLinus Torvalds <torvalds@g5.osdl.org>2006-04-18 19:49:42 -0700
commit038e5e2bf2819058fb1b4b52b583bef9ad063356 (patch)
tree3a152b455f845a25d0958af5b461b034c2d565fa /arch/mips/mips-boards/atlas/atlas_int.c
parent5c723d26fa223bdb17b9230c77e4e1156884475a (diff)
parentd34cb28a3718a7055ed14e2ec058fe3e4574af63 (diff)
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (47 commits) [MAINTAINERS] The ham radio code now has website at http://www.linux-ax25.org. [MIPS] Use __ffs() instead of ffs() for waybit calculation. [MIPS] Fix Makefile bugs for MIPS32/MIPS64 R1 and R2. [MIPS] Handle IDE PIO cache aliases on SMP. [MIPS] Make mips_srs_init static. [MIPS] MIPS boards: Set HZ to 100. [MIPS] kgdb: Let gcc compute the array size itself. [MIPS] FPU affinity for MT ASE. [MIPS] MT: Improved multithreading support. [MIPS] kpsd and other AP/SP improvements. [MIPS] R2: Instruction hazard barrier. [MIPS] Fix genrtc compilation. [MIPS] R2: Implement shadow register allocation without spinlock. [MIPS] Fix VR41xx build errors. [MIPS] Fix tx49_blast_icache32_page_indexed. [MIPS] Enable SCHED_NO_NO_OMIT_FRAME_POINTER for MIPS. [MIPS] Use "R" constraint for cache_op. [MIPS] Rewrite all the assembler interrupt handlers to C. [MIPS] Fix the crime against humanity that mipsIRQ.S is. [MIPS] Fixup damage done by 22a9835c350782a5c3257343713932af3ac92ee0. ...
Diffstat (limited to 'arch/mips/mips-boards/atlas/atlas_int.c')
-rw-r--r--arch/mips/mips-boards/atlas/atlas_int.c92
1 files changed, 86 insertions, 6 deletions
diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c
index bc0ebc69bfb3..db53950b7cfb 100644
--- a/arch/mips/mips-boards/atlas/atlas_int.c
+++ b/arch/mips/mips-boards/atlas/atlas_int.c
@@ -39,8 +39,6 @@
static struct atlas_ictrl_regs *atlas_hw0_icregs;
-extern asmlinkage void mipsIRQ(void);
-
#if 0
#define DEBUG_INT(x...) printk(x)
#else
@@ -98,7 +96,7 @@ static inline int ls1bit32(unsigned int x)
return b;
}
-void atlas_hw0_irqdispatch(struct pt_regs *regs)
+static inline void atlas_hw0_irqdispatch(struct pt_regs *regs)
{
unsigned long int_status;
int irq;
@@ -116,6 +114,91 @@ void atlas_hw0_irqdispatch(struct pt_regs *regs)
do_IRQ(irq, regs);
}
+static inline int clz(unsigned long x)
+{
+ __asm__ (
+ " .set push \n"
+ " .set mips32 \n"
+ " clz %0, %1 \n"
+ " .set pop \n"
+ : "=r" (x)
+ : "r" (x));
+
+ return x;
+}
+
+/*
+ * Version of ffs that only looks at bits 12..15.
+ */
+static inline unsigned int irq_ffs(unsigned int pending)
+{
+#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
+ return -clz(pending) + 31 - CAUSEB_IP;
+#else
+ unsigned int a0 = 7;
+ unsigned int t0;
+
+ t0 = s0 & 0xf000;
+ t0 = t0 < 1;
+ t0 = t0 << 2;
+ a0 = a0 - t0;
+ s0 = s0 << t0;
+
+ t0 = s0 & 0xc000;
+ t0 = t0 < 1;
+ t0 = t0 << 1;
+ a0 = a0 - t0;
+ s0 = s0 << t0;
+
+ t0 = s0 & 0x8000;
+ t0 = t0 < 1;
+ //t0 = t0 << 2;
+ a0 = a0 - t0;
+ //s0 = s0 << t0;
+
+ return a0;
+#endif
+}
+
+/*
+ * IRQs on the Atlas board look basically (barring software IRQs which we
+ * don't use at all and all external interrupt sources are combined together
+ * on hardware interrupt 0 (MIPS IRQ 2)) like:
+ *
+ * MIPS IRQ Source
+ * -------- ------
+ * 0 Software (ignored)
+ * 1 Software (ignored)
+ * 2 Combined hardware interrupt (hw0)
+ * 3 Hardware (ignored)
+ * 4 Hardware (ignored)
+ * 5 Hardware (ignored)
+ * 6 Hardware (ignored)
+ * 7 R4k timer (what we use)
+ *
+ * We handle the IRQ according to _our_ priority which is:
+ *
+ * Highest ---- R4k Timer
+ * Lowest ---- Combined hardware interrupt
+ *
+ * then we just return, if multiple IRQs are pending then we will just take
+ * another exception, big deal.
+ */
+asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
+{
+ unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
+ int irq;
+
+ irq = irq_ffs(pending);
+
+ if (irq == MIPSCPU_INT_ATLAS)
+ atlas_hw0_irqdispatch(regs);
+ else if (irq > 0)
+ do_IRQ(MIPSCPU_INT_BASE + irq, regs);
+ else
+ spurious_interrupt(regs);
+}
+
void __init arch_init_irq(void)
{
int i;
@@ -128,9 +211,6 @@ void __init arch_init_irq(void)
*/
atlas_hw0_icregs->intrsten = 0xffffffff;
- /* Now safe to set the exception vector. */
- set_except_vector(0, mipsIRQ);
-
for (i = ATLASINT_BASE; i <= ATLASINT_END; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;