diff options
| author | Florian Fainelli <f.fainelli@gmail.com> | 2016-04-04 10:55:36 -0700 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-05-10 10:25:41 +0200 |
| commit | 93e27aae8460e464e04cf5cfa387bac8947f941a (patch) | |
| tree | ccc31e14b228152854a90069036a7af39c56de9c /arch/mips/mm/c-r4k.c | |
| parent | 3ab4cbdf079226f4ee97bc95f6bd8f8d498eb6c3 (diff) | |
MIPS: BMIPS: local_r4k___flush_cache_all needs to blast S-cache
commit f675843ddfdfdf467d08cc922201614a149e439e upstream.
local_r4k___flush_cache_all() is missing a special check for BMIPS5000
processors, we need to blast the S-cache, just like other MTI processors
since we have an inclusive cache. We also need an additional __sync() to
make sure this is completed.
Fixes: d74b0172e4e2c ("MIPS: BMIPS: Add special cache handling in c-r4k.c")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13012/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/mips/mm/c-r4k.c')
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 9d64559649da..6c0147bd8e80 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -447,6 +447,11 @@ static inline void local_r4k___flush_cache_all(void * args) r4k_blast_scache(); break; + case CPU_BMIPS5000: + r4k_blast_scache(); + __sync(); + break; + default: r4k_blast_dcache(); r4k_blast_icache(); |