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authorRalf Baechle <ralf@linux-mips.org>2014-05-22 09:55:02 +0200
committerRalf Baechle <ralf@linux-mips.org>2014-05-23 15:12:38 +0200
commitc836732fa058a62bb8f30a7a03f776f6c488fa58 (patch)
tree2d970152b6cf195b22088d2f7a1fe52890c92012 /arch/mips/mm/c-r4k.c
parent70e4c234aa48e11c0575364939dfab4cb27b2172 (diff)
MIPS: c-r4k: Call R4600_HIT_CACHEOP_WAR_IMPL only for 32 byte cache lines.
R4600_HIT_CACHEOP_WAR_IMPL is only needed on R4600 v1.6 and the R4600 has data cache lines that are always 32 bytes so the call is pointless in r4k_blast_dcache_page_dc64. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/c-r4k.c')
-rw-r--r--arch/mips/mm/c-r4k.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 1c74a6ad072a..7bc14ffc7a1c 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -105,7 +105,6 @@ static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
{
- R4600_HIT_CACHEOP_WAR_IMPL;
blast_dcache64_page(addr);
}