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authorManuel Lauss <manuel.lauss@gmail.com>2014-07-23 16:36:51 +0200
committerRalf Baechle <ralf@linux-mips.org>2014-07-30 14:09:42 +0200
commit8e21170581d99038c41c803af289e1a6491cb145 (patch)
tree81a4d1e8499a6b3c8902bb24fa7e797fc5ff0240 /arch/mips/pci
parent3feae78416ae2c30f12c0a4bbe2e5dddf029510d (diff)
MIPS: Alchemy: pci: use clk framework to enable PCI clock
Use the clock framework to get at the PCI clock source and enable it on driver initialization. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/7471/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/pci')
-rw-r--r--arch/mips/pci/pci-alchemy.c24
1 files changed, 23 insertions, 1 deletions
diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c
index 563d1f61d6ee..c19600a03460 100644
--- a/arch/mips/pci/pci-alchemy.c
+++ b/arch/mips/pci/pci-alchemy.c
@@ -7,6 +7,7 @@
* Support for all devices (greater than 16) added by David Gathright.
*/
+#include <linux/clk.h>
#include <linux/export.h>
#include <linux/types.h>
#include <linux/pci.h>
@@ -364,6 +365,7 @@ static int alchemy_pci_probe(struct platform_device *pdev)
void __iomem *virt_io;
unsigned long val;
struct resource *r;
+ struct clk *c;
int ret;
/* need at least PCI IRQ mapping table */
@@ -393,11 +395,24 @@ static int alchemy_pci_probe(struct platform_device *pdev)
goto out1;
}
+ c = clk_get(&pdev->dev, "pci_clko");
+ if (IS_ERR(c)) {
+ dev_err(&pdev->dev, "unable to find PCI clock\n");
+ ret = PTR_ERR(c);
+ goto out2;
+ }
+
+ ret = clk_prepare_enable(c);
+ if (ret) {
+ dev_err(&pdev->dev, "cannot enable PCI clock\n");
+ goto out6;
+ }
+
ctx->regs = ioremap_nocache(r->start, resource_size(r));
if (!ctx->regs) {
dev_err(&pdev->dev, "cannot map pci regs\n");
ret = -ENODEV;
- goto out2;
+ goto out5;
}
/* map parts of the PCI IO area */
@@ -465,12 +480,19 @@ static int alchemy_pci_probe(struct platform_device *pdev)
register_syscore_ops(&alchemy_pci_pmops);
register_pci_controller(&ctx->alchemy_pci_ctrl);
+ dev_info(&pdev->dev, "PCI controller at %ld MHz\n",
+ clk_get_rate(c) / 1000000);
+
return 0;
out4:
iounmap(virt_io);
out3:
iounmap(ctx->regs);
+out5:
+ clk_disable_unprepare(c);
+out6:
+ clk_put(c);
out2:
release_mem_region(r->start, resource_size(r));
out1: