diff options
| author | Scott Wood <scottwood@freescale.com> | 2013-07-23 20:21:11 -0500 |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2013-08-20 15:45:49 -0500 |
| commit | d52459ca3047435aa5d7957e50857fc7ba193411 (patch) | |
| tree | b0e14ee68283d438d4ee5baa89d4a652f753a8b2 /arch/powerpc/include/asm/reg.h | |
| parent | afbcdd97bf117bc2d01b865a32f78f662437a4d8 (diff) | |
powerpc/fsl-booke: Work around erratum A-006958
Erratum A-006598 says that 64-bit mftb is not atomic -- it's subject
to a similar race condition as doing mftbu/mftbl on 32-bit. The lower
half of timebase is updated before the upper half; thus, we can share
the workaround for a similar bug on Cell. This workaround involves
looping if the lower half of timebase is zero, thus avoiding the need
for a scratch register (other than CR0). This workaround must be
avoided when the timebase is frozen, such as during the timebase sync
code.
This deals with kernel and vdso accesses, but other userspace accesses
will of course need to be fixed elsewhere.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'arch/powerpc/include/asm/reg.h')
| -rw-r--r-- | arch/powerpc/include/asm/reg.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index a312e0c8cef4..55b03079d197 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -1117,7 +1117,7 @@ : "memory") #ifdef __powerpc64__ -#ifdef CONFIG_PPC_CELL +#if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E) #define mftb() ({unsigned long rval; \ asm volatile( \ "90: mftb %0;\n" \ |