diff options
| author | Cyril Bur <cyrilbur@gmail.com> | 2016-09-14 18:02:16 +1000 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2016-10-04 20:33:17 +1100 |
| commit | 5d176f751ee3c6eededd984ad409bff201f436a7 (patch) | |
| tree | c760a51812c2cfd6c27fccf9bd0f4d303e984509 /arch/powerpc/kernel/traps.c | |
| parent | 172f7aaa75d0eaae167edde25c08aae9059e80fc (diff) | |
powerpc: tm: Enable transactional memory (TM) lazily for userspace
Currently the MSR TM bit is always set if the hardware is TM capable.
This adds extra overhead as it means the TM SPRS (TFHAR, TEXASR and
TFAIR) must be swapped for each process regardless of if they use TM.
For processes that don't use TM the TM MSR bit can be turned off
allowing the kernel to avoid the expensive swap of the TM registers.
A TM unavailable exception will occur if a thread does use TM and the
kernel will enable MSR_TM and leave it so for some time afterwards.
Signed-off-by: Cyril Bur <cyrilbur@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/kernel/traps.c')
| -rw-r--r-- | arch/powerpc/kernel/traps.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c index 2f5ef5a80353..a1f8f5641e9e 100644 --- a/arch/powerpc/kernel/traps.c +++ b/arch/powerpc/kernel/traps.c @@ -1392,6 +1392,15 @@ void vsx_unavailable_exception(struct pt_regs *regs) #ifdef CONFIG_PPC64 static void tm_unavailable(struct pt_regs *regs) { +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + if (user_mode(regs)) { + current->thread.load_tm++; + regs->msr |= MSR_TM; + tm_enable(); + tm_restore_sprs(¤t->thread); + return; + } +#endif pr_emerg("Unrecoverable TM Unavailable Exception " "%lx at %lx\n", regs->trap, regs->nip); die("Unrecoverable TM Unavailable Exception", regs, SIGABRT); |