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authorStefan Roese <sr@denx.de>2008-04-02 00:45:00 +1100
committerJosh Boyer <jwboyer@linux.vnet.ibm.com>2008-04-02 20:29:30 -0500
commit5f91925c89c39e77c170de9366ffa5144a8dd8ec (patch)
tree755bccb9a58514900bc8e800550311ea61979297 /arch/powerpc/sysdev/ppc4xx_pci.c
parentb64c4c937daaa04a0a5c188718fb77e8041b5686 (diff)
[POWERPC] 4xx: Fix PESDRn_UTLSET1 register setup on 460EX/GT
The patch fixes a bug, where the PESDRn_UTLSET1 register was setup wrongly resulting in a non working PCIe port 1. With this fix both PCIe ports work fine again. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'arch/powerpc/sysdev/ppc4xx_pci.c')
-rw-r--r--arch/powerpc/sysdev/ppc4xx_pci.c10
1 files changed, 4 insertions, 6 deletions
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c
index aa856ea9fed8..1814adbd2236 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.c
+++ b/arch/powerpc/sysdev/ppc4xx_pci.c
@@ -785,19 +785,17 @@ static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
u32 val;
u32 utlset1;
- if (port->endpoint) {
+ if (port->endpoint)
val = PTYPE_LEGACY_ENDPOINT << 20;
- utlset1 = 0x20222222;
- } else {
+ else
val = PTYPE_ROOT_PORT << 20;
- utlset1 = 0x21222222;
- }
if (port->index == 0) {
val |= LNKW_X1 << 12;
+ utlset1 = 0x20000000;
} else {
val |= LNKW_X4 << 12;
- utlset1 |= 0x00101101;
+ utlset1 = 0x20101101;
}
mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);