diff options
| author | Stephane Eranian <eranian@google.com> | 2020-11-26 20:09:22 +0900 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-12-30 11:50:57 +0100 |
| commit | a803ea15b0dca8f073b3d5139b962a0a93354e00 (patch) | |
| tree | 9e2426e5d41fbab3442fe2ad9319d3e28110d674 /arch/x86/events | |
| parent | 12db619c91d78d3db7e8cd05147108ed1eaa4783 (diff) | |
perf/x86/intel: Check PEBS status correctly
[ Upstream commit fc17db8aa4c53cbd2d5469bb0521ea0f0a6dbb27 ]
The kernel cannot disambiguate when 2+ PEBS counters overflow at the
same time. This is what the comment for this code suggests. However,
I see the comparison is done with the unfiltered p->status which is a
copy of IA32_PERF_GLOBAL_STATUS at the time of the sample. This
register contains more than the PEBS counter overflow bits. It also
includes many other bits which could also be set.
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Signed-off-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20201126110922.317681-2-namhyung@kernel.org
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'arch/x86/events')
| -rw-r--r-- | arch/x86/events/intel/ds.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 1aaba2c8a9ba..eb8bd0eeace7 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -1912,7 +1912,7 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs) * that caused the PEBS record. It's called collision. * If collision happened, the record will be dropped. */ - if (p->status != (1ULL << bit)) { + if (pebs_status != (1ULL << bit)) { for_each_set_bit(i, (unsigned long *)&pebs_status, size) error[i]++; continue; |