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authorAndi Kleen <andi@firstfloor.org>2009-07-09 00:31:45 +0200
committerH. Peter Anvin <hpa@zytor.com>2009-07-09 18:39:47 -0700
commit3ccdccfadbd2548abe38682b587f4ba27eac2fc9 (patch)
tree3ee1c1f850409cffad35464dfc310d242dd66d25 /arch/x86/include/asm/mce.h
parenta2d32bcbc008aa0f9c301a7c6f3494cb23e6af54 (diff)
x86: mce: Lower maximum number of banks to architecture limit
The Intel x86 architecture right now only supports 32 machine check banks, more would bump into other MSRs. So lower the max define to 32. This only affects a few bitmaps, most data structures are dynamically sized anyways. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/x86/include/asm/mce.h')
-rw-r--r--arch/x86/include/asm/mce.h7
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 6b8a974e1270..ad7535372918 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -130,10 +130,11 @@ void mce_log(struct mce *m);
DECLARE_PER_CPU(struct sys_device, mce_dev);
/*
- * To support more than 128 would need to escape the predefined
- * Linux defined extended banks first.
+ * Maximum banks number.
+ * This is the limit of the current register layout on
+ * Intel CPUs.
*/
-#define MAX_NR_BANKS (MCE_EXTENDED_BANK - 1)
+#define MAX_NR_BANKS 32
#ifdef CONFIG_X86_MCE_INTEL
extern int mce_cmci_disabled;