diff options
| author | Andi Kleen <andi@firstfloor.org> | 2009-02-12 13:49:35 +0100 |
|---|---|---|
| committer | H. Peter Anvin <hpa@zytor.com> | 2009-02-24 13:41:00 -0800 |
| commit | 03195c6b40f2b4db92545921daa7c3a19b4e4c32 (patch) | |
| tree | 895b6a502a4cfe05e4c667f7eb093b74eecef31c /arch/x86/include/asm/mce.h | |
| parent | ee031c31d6381d004bfd386c2e45821211507499 (diff) | |
x86, mce, cmci: define MSR names and fields for new CMCI registers
Impact: New register definitions only
CMCI means support for raising an interrupt on a corrected machine
check event instead of having to poll for it. It's a new feature in
Intel Nehalem CPUs available on some machine check banks.
For details see the IA32 SDM Vol3a 14.5
Define the registers for it as a preparation for further patches.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/x86/include/asm/mce.h')
| -rw-r--r-- | arch/x86/include/asm/mce.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 9b9523699dbc..6fc5e07eca4f 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -11,6 +11,8 @@ */ #define MCG_CTL_P (1UL<<8) /* MCG_CAP register available */ +#define MCG_EXT_P (1ULL<<9) /* Extended registers available */ +#define MCG_CMCI_P (1ULL<<10) /* CMCI supported */ #define MCG_STATUS_RIPV (1UL<<0) /* restart ip valid */ #define MCG_STATUS_EIPV (1UL<<1) /* ip points to correct instruction */ |