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authorMatt Wagner <mwagner@nvidia.com>2011-04-05 17:17:38 -0700
committerVarun Colbert <vcolbert@nvidia.com>2011-04-07 16:49:35 -0700
commit6fa92df36af66330bb1939b1ec8016df6e9b51b3 (patch)
treef366ad436fa0e1ed17e6ca06de53e6a239ec8742 /arch
parentbc2c69ec2a686e2064a7b28169aa0fd908afc90f (diff)
ARM: tegra: Limit host1x clock for AP20 SKUs
This changes the max frequency of the host1x clock to 108Mhz as in K32 in order to allow core voltage drop to 1000mV. Bug 779576 Change-Id: I71b6eff72462a32da5b4e622dbb6fe5032b2b7e6 Reviewed-on: http://git-master/r/24851 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-tegra/tegra2_clocks.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 3777b2a9a43b..8a9a4036540c 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -2207,6 +2207,8 @@ static struct tegra_sku_rate_limit sku_limits[] =
RATE_LIMIT("vde", 240000000, 0x04, 0x7, 0x08, 0x0F, 0x10),
RATE_LIMIT("3d", 300000000, 0x04, 0x7, 0x08, 0x0F, 0x10),
+ RATE_LIMIT("host1x", 108000000, 0x0F),
+
RATE_LIMIT("sclk", 300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
RATE_LIMIT("hclk", 300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
RATE_LIMIT("avp.sclk", 300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),