diff options
| author | Seshendra Gadagottu <sgadagottu@nvidia.com> | 2011-03-13 12:13:28 +0530 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2011-04-01 19:25:37 -0700 |
| commit | e09e4554f46532b1bea0f13d444e81efbb361fff (patch) | |
| tree | 5e5716415d09f3a920a28c19520989a6a9474d60 /arch | |
| parent | 3232571484990077caf807d389a5ca002e14920f (diff) | |
ARM: tegra: usb_phy: Setting USB_TXFILLTUNING for underrun issue
Setting the USB_TXFILLTUNING to 0x10, where as power on value
is 0x2. With this updated setting USB2 controller under run
are avoided. Setting this value after power_on and post_resume.
Bug 791857
Change-Id: I10ed644ee90d4bc119562699c624568b3a868942
Reviewed-on: http://git-master/r/22735
Reviewed-on: http://git-master/r/23183
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-tegra/usb_phy.c | 32 |
1 files changed, 31 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c index 64ff9492a8bb..376142a8a546 100644 --- a/arch/arm/mach-tegra/usb_phy.c +++ b/arch/arm/mach-tegra/usb_phy.c @@ -42,6 +42,10 @@ #define USB_USBSTS_PCI (1 << 2) #define USB_USBSTS_HCH (1 << 12) +#define USB_TXFILLTUNING 0x164 +#define USB_FIFO_TXFILL_THRES(x) (((x) & 0x1f) << 16) +#define USB_FIFO_TXFILL_MASK 0x1f0000 + #define ULPI_VIEWPORT 0x170 #define USB_PORTSC1 0x184 @@ -699,6 +703,19 @@ static void utmi_phy_postresume(struct tegra_usb_phy *phy) writel(val, base + UTMIP_TX_CFG0); } +static void uhsic_phy_postresume(struct tegra_usb_phy *phy) +{ + unsigned long val; + void __iomem *base = phy->regs; + + val = readl(base + USB_TXFILLTUNING); + if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) { + val = USB_FIFO_TXFILL_THRES(0x10); + writel(val, base + USB_TXFILLTUNING); + } + +} + static void utmi_phy_restore_start(struct tegra_usb_phy *phy, enum tegra_usb_phy_port_speed port_speed) { @@ -979,6 +996,12 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *phy) val &= ~USB_PORTSC1_PTS(~0); writel(val, base + USB_PORTSC1); + val = readl(base + USB_TXFILLTUNING); + if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) { + val = USB_FIFO_TXFILL_THRES(0x10); + writel(val, base + USB_TXFILLTUNING); + } + val = readl(base + USB_PORTSC1); val &= ~(USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN); writel(val, base + USB_PORTSC1); @@ -1189,8 +1212,15 @@ void tegra_usb_phy_preresume(struct tegra_usb_phy *phy) void tegra_usb_phy_postresume(struct tegra_usb_phy *phy) { - if (!phy_is_ulpi(phy)) + struct tegra_ulpi_config *config = phy->config; + + if ((phy->instance == 1) && + (config->inf_type == TEGRA_USB_UHSIC)) + uhsic_phy_postresume(phy); + else if (!phy_is_ulpi(phy)) utmi_phy_postresume(phy); + + return 0; } void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy, |