ENGR00132832-1 MX50 SSI: fix ssi errors caused by mx5 dual fifo enable

Upgrade SDMA script to support SSIs dual fifo breaks mx50 ssi, because
mx50 new script not available yet.

Fix it by according to cpu model to set correct sdma script address.

Signed-off-by: Zeng Zhaoming <b32542@freescale.com>

2 files changed, 97 insertions, 11 deletions

diff --git a/arch/arm/mach-mx5/dma.c b/arch/arm/mach-mx5/dma.c
index 2a2108966913..aec79d5a96bb 100644
--- a/arch/arm/mach-mx5/dma.c
+++ b/arch/arm/mach-mx5/dma.c
@@ -1371,13 +1371,95 @@ static int __init dma_fixups(void)
 	mxc_sdma_spdif_16bit_tx_params.chnl_params.event_id = DMA_REQ_SPDIF_TX;
 	mxc_sdma_spdif_32bit_tx_params.chnl_params.event_id = DMA_REQ_SPDIF_TX;
 
-	mxc_sdma_ssi3_8bit_tx1_params.chnl_params.event_id =
-						DMA_REQ_SSI3_TX2_MX53;
-	mxc_sdma_ssi3_16bit_tx1_params.chnl_params.event_id =
-						DMA_REQ_SSI3_TX2_MX53;
-	mxc_sdma_ssi3_24bit_tx1_params.chnl_params.event_id =
-						DMA_REQ_SSI3_TX2_MX53;
-
+	if (cpu_is_mx53()) {
+		mxc_sdma_ssi3_8bit_tx1_params.chnl_params.event_id =
+							DMA_REQ_SSI3_TX2_MX53;
+		mxc_sdma_ssi3_16bit_tx1_params.chnl_params.event_id =
+							DMA_REQ_SSI3_TX2_MX53;
+		mxc_sdma_ssi3_24bit_tx1_params.chnl_params.event_id =
+							DMA_REQ_SSI3_TX2_MX53;
+	} else if (cpu_is_mx50()) {
+		/* mx50 not support double fifo */
+#ifdef CONFIG_MXC_SSI_DUAL_FIFO
+		u32 tx_wm = MXC_SSI_TXFIFO_WML/2;
+		u32 rx_wm = MXC_SSI_RXFIFO_WML/2;
+#else
+		u32 tx_wm = MXC_SSI_TXFIFO_WML;
+		u32 rx_wm = MXC_SSI_RXFIFO_WML;
+#endif
+		mxc_sdma_ssi1_8bit_tx0_params.chnl_params.watermark_level =
+						tx_wm;
+		mxc_sdma_ssi1_8bit_rx0_params.chnl_params.watermark_level =
+						rx_wm;
+		mxc_sdma_ssi1_16bit_tx0_params.chnl_params.watermark_level =
+						tx_wm;
+		mxc_sdma_ssi1_16bit_rx0_params.chnl_params.watermark_level =
+						rx_wm;
+		mxc_sdma_ssi1_24bit_tx0_params.chnl_params.watermark_level =
+						tx_wm;
+		mxc_sdma_ssi1_24bit_rx0_params.chnl_params.watermark_level =
+						rx_wm;
+		mxc_sdma_ssi1_8bit_tx1_params.chnl_params.watermark_level =
+						tx_wm;
+		mxc_sdma_ssi1_8bit_rx1_params.chnl_params.watermark_level =
+						rx_wm;
+		mxc_sdma_ssi1_16bit_tx1_params.chnl_params.watermark_level =
+						tx_wm;
+		mxc_sdma_ssi1_16bit_rx1_params.chnl_params.watermark_level =
+						rx_wm;
+		mxc_sdma_ssi1_24bit_tx1_params.chnl_params.watermark_level =
+						tx_wm;
+		mxc_sdma_ssi1_24bit_rx1_params.chnl_params.watermark_level =
+						rx_wm;
+		mxc_sdma_ssi2_8bit_tx0_params.chnl_params.watermark_level =
+						tx_wm;
+		mxc_sdma_ssi2_8bit_rx0_params.chnl_params.watermark_level =
+						rx_wm;
+		mxc_sdma_ssi2_16bit_tx0_params.chnl_params.watermark_level =
+						tx_wm;
+		mxc_sdma_ssi2_16bit_rx0_params.chnl_params.watermark_level =
+						rx_wm;
+		mxc_sdma_ssi2_24bit_tx0_params.chnl_params.watermark_level =
+						tx_wm;
+		mxc_sdma_ssi2_24bit_rx0_params.chnl_params.watermark_level =
+						rx_wm;
+		mxc_sdma_ssi2_8bit_tx1_params.chnl_params.watermark_level =
+						tx_wm;
+		mxc_sdma_ssi2_8bit_rx1_params.chnl_params.watermark_level =
+						rx_wm;
+		mxc_sdma_ssi2_16bit_tx1_params.chnl_params.watermark_level =
+						tx_wm;
+		mxc_sdma_ssi2_16bit_rx1_params.chnl_params.watermark_level =
+						rx_wm;
+		mxc_sdma_ssi2_24bit_tx1_params.chnl_params.watermark_level =
+						tx_wm;
+		mxc_sdma_ssi2_24bit_rx1_params.chnl_params.watermark_level =
+						rx_wm;
+		mxc_sdma_ssi3_8bit_tx0_params.chnl_params.watermark_level =
+						tx_wm;
+		mxc_sdma_ssi3_8bit_rx0_params.chnl_params.watermark_level =
+						rx_wm;
+		mxc_sdma_ssi3_16bit_tx0_params.chnl_params.watermark_level =
+						tx_wm;
+		mxc_sdma_ssi3_16bit_rx0_params.chnl_params.watermark_level =
+						rx_wm;
+		mxc_sdma_ssi3_24bit_tx0_params.chnl_params.watermark_level =
+						tx_wm;
+		mxc_sdma_ssi3_24bit_rx0_params.chnl_params.watermark_level =
+						rx_wm;
+		mxc_sdma_ssi3_8bit_tx1_params.chnl_params.watermark_level =
+						tx_wm;
+		mxc_sdma_ssi3_8bit_rx1_params.chnl_params.watermark_level =
+						rx_wm;
+		mxc_sdma_ssi3_16bit_tx1_params.chnl_params.watermark_level =
+						tx_wm;
+		mxc_sdma_ssi3_16bit_rx1_params.chnl_params.watermark_level =
+						rx_wm;
+		mxc_sdma_ssi3_24bit_tx1_params.chnl_params.watermark_level =
+						tx_wm;
+		mxc_sdma_ssi3_24bit_rx1_params.chnl_params.watermark_level =
+						rx_wm;
+	}
 	return 0;
 }
 arch_initcall(dma_fixups);
diff --git a/arch/arm/plat-mxc/sdma/sdma.c b/arch/arm/plat-mxc/sdma/sdma.c
index a8191dabc4b3..7fa3cb8582f1 100644
--- a/arch/arm/plat-mxc/sdma/sdma.c
+++ b/arch/arm/plat-mxc/sdma/sdma.c
@@ -304,7 +304,9 @@ static unsigned short sdma_get_pc(sdma_periphT peripheral_type,
 			res = -EINVAL;
 		}
 #ifdef CONFIG_MXC_SSI_DUAL_FIFO
-	} else if (peripheral_type == CSPI || peripheral_type == EXT) {
+	} else if (peripheral_type == CSPI || peripheral_type == EXT ||
+		   (peripheral_type == SSI &&
+		   !(cpu_is_mx51() || cpu_is_mx53()))) {
 #else
 	} else if (peripheral_type == CSPI || peripheral_type == EXT ||
 		   peripheral_type == SSI) {
@@ -326,9 +328,11 @@ static unsigned short sdma_get_pc(sdma_periphT peripheral_type,
 			res = -EINVAL;
 		}
 #ifdef CONFIG_MXC_SSI_DUAL_FIFO
-	} else if (peripheral_type == MMC ||
-		   peripheral_type == SDHC || peripheral_type == CSPI_SP ||
-		   peripheral_type == ESAI || peripheral_type == MSHC_SP) {
+	} else if (peripheral_type == MMC || peripheral_type == SDHC ||
+		   peripheral_type == CSPI_SP || peripheral_type == ESAI ||
+		   peripheral_type == MSHC_SP ||
+		   (peripheral_type == SSI_SP &&
+		   !(cpu_is_mx51() || cpu_is_mx53()))) {
 #else
 	} else if (peripheral_type == SSI_SP || peripheral_type == MMC ||
 		   peripheral_type == SDHC || peripheral_type == CSPI_SP ||