diff options
| author | Jason Chen <b02280@freescale.com> | 2010-11-18 16:17:32 +0800 |
|---|---|---|
| committer | Justin Waters <justin.waters@timesys.com> | 2010-12-14 10:40:53 -0500 |
| commit | 7e5ffcdb9f59ec09d298c32f3e1a4a5da6e8cdcb (patch) | |
| tree | 9a2a509a9e12b75e238459bc4b3528456eea6467 /arch | |
| parent | 637af9d9d4d51d4ae25d632e61991075056d6053 (diff) | |
ENGR00133848 imx51 MSL uart: change uart default parent to pll2
change uart default parent to pll2 and clk rate to 66.5MHz
Signed-off-by: Jason Chen <b02280@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-mx5/clock.c | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/arch/arm/mach-mx5/clock.c b/arch/arm/mach-mx5/clock.c index 746387092106..783d97351497 100644 --- a/arch/arm/mach-mx5/clock.c +++ b/arch/arm/mach-mx5/clock.c @@ -4660,17 +4660,14 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long (0 << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET); __raw_writel(reg, MXC_CCM_CSCDR1); } else { - /* Move UART to run from PLL3 */ - clk_set_parent(&uart_main_clk, &pll3_sw_clk); + clk_set_parent(&uart_main_clk, &pll2_sw_clk); - /* Set the UART dividers to divide, - * so the UART_CLK is 66.5MHz. - */ + /* Set the UART dividers to divide, so the UART_CLK is 66.5MHz. */ reg = __raw_readl(MXC_CCM_CSCDR1); reg &= ~MXC_CCM_CSCDR1_UART_CLK_PODF_MASK; reg &= ~MXC_CCM_CSCDR1_UART_CLK_PRED_MASK; - reg |= (3 << MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) | - (0 << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET); + reg |= (4 << MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) | + (1 << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET); __raw_writel(reg, MXC_CCM_CSCDR1); } |